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genlib/cdc: add ElasticBuffer
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enjoy-digital committed Oct 13, 2016
1 parent b730caf commit 15c0d1c
Showing 1 changed file with 45 additions and 1 deletion.
46 changes: 45 additions & 1 deletion migen/genlib/cdc.py
Original file line number Diff line number Diff line change
@@ -4,9 +4,10 @@

from migen.fhdl.structure import *
from migen.fhdl.module import Module
from migen.fhdl.specials import Special
from migen.fhdl.specials import Special, Memory
from migen.fhdl.bitcontainer import value_bits_sign
from migen.genlib.misc import WaitTimer
from migen.genlib.resetsync import AsyncResetSynchronizer


class NoRetiming(Special):
@@ -157,3 +158,46 @@ def __init__(self, width):
for i in reversed(range(width-1)):
self.comb += o_comb[i].eq(o_comb[i+1] ^ self.i[i])
self.sync += self.o.eq(o_comb)


class ElasticBuffer(Module):
def __init__(self, width, depth, idomain, odomain):
self.reset = Signal()
self.din = Signal(width)
self.dout = Signal(width)

# # #

cd_write = ClockDomain()
cd_read = ClockDomain()
self.comb += [
cd_write.clk.eq(ClockSignal(idomain)),
cd_read.clk.eq(ClockSignal(odomain))
]
self.specials += [
AsyncResetSynchronizer(cd_write, self.reset),
AsyncResetSynchronizer(cd_read, self.reset)
]
self.clock_domains += cd_write, cd_read

wrpointer = Signal(max=depth, reset=depth//2)
rdpointer = Signal(max=depth)

storage = Memory(width, depth)
self.specials += storage

wrport = storage.get_port(write_capable=True, clock_domain="write")
rdport = storage.get_port(clock_domain="read")
self.specials += wrport, rdport

self.sync.write += wrpointer.eq(wrpointer + 1)
self.sync.read += rdpointer.eq(rdpointer + 1)

self.comb += [
wrport.we.eq(1),
wrport.adr.eq(wrpointer),
wrport.dat_w.eq(self.din),

rdport.adr.eq(rdpointer),
self.dout.eq(rdport.dat_r)
]

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