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base repository: m-labs/artiq
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  • 8 commits
  • 7 files changed
  • 1 contributor

Commits on Sep 27, 2016

  1. kc705: single ended rtio_external_clk

    use single ended user_sma_clk_n instead of p/n to free up one clock sma
    jordens committed Sep 27, 2016
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    a9426d9 View commit details
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    7f0dffd View commit details
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    740b61a View commit details

Commits on Sep 28, 2016

  1. phase: wire up clocking differently

    needs patched misoc
    jordens committed Sep 28, 2016
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    ad9cc45 View commit details
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    8dc7825 View commit details
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    d500288 View commit details

Commits on Sep 29, 2016

  1. phaser: spi tweaks

    jordens committed Sep 29, 2016
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    9490be3 View commit details
  2. ad9516: some startup

    jordens committed Sep 29, 2016
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Showing with 62 additions and 12 deletions.
  1. +4 −8 artiq/gateware/targets/kc705.py
  2. +1 −2 artiq/runtime/ad9154.c
  3. +2 −0 artiq/runtime/ad9154.h
  4. +1 −1 artiq/runtime/ad9516.c
  5. +2 −0 artiq/runtime/ad9516.h
  6. +1 −1 artiq/runtime/ad9516_reg.h
  7. +51 −0 artiq/runtime/test_mode.c
12 changes: 4 additions & 8 deletions artiq/gateware/targets/kc705.py
Original file line number Diff line number Diff line change
@@ -39,13 +39,6 @@ def __init__(self, platform, rtio_internal_clk):
self.sync.ext_clkout += ext_clkout.eq(~ext_clkout)


rtio_external_clk = Signal()
user_sma_clock = platform.request("user_sma_clock")
platform.add_period_constraint(user_sma_clock.p, 8.0)
self.specials += Instance("IBUFDS",
i_I=user_sma_clock.p, i_IB=user_sma_clock.n,
o_O=rtio_external_clk)

pll_locked = Signal()
rtio_clk = Signal()
rtiox4_clk = Signal()
@@ -56,7 +49,7 @@ def __init__(self, platform, rtio_internal_clk):

p_REF_JITTER1=0.01,
p_CLKIN1_PERIOD=8.0, p_CLKIN2_PERIOD=8.0,
i_CLKIN1=rtio_internal_clk, i_CLKIN2=rtio_external_clk,
i_CLKIN1=rtio_internal_clk, i_CLKIN2=0,
# Warning: CLKINSEL=0 means CLKIN2 is selected
i_CLKINSEL=~self._clock_sel.storage,

@@ -401,6 +394,9 @@ def __init__(self, cpu_type="or1k", **kwargs):
platform = self.platform
platform.add_extension(phaser.fmc_adapter_io)

user_sma_clock = platform.request("user_sma_clock_p")
self.comb += user_sma_clock.eq(self.crg.clk200_se)

rtio_channels = []

phy = ttl_serdes_7series.Inout_8X(
3 changes: 1 addition & 2 deletions artiq/runtime/ad9154.c
Original file line number Diff line number Diff line change
@@ -5,7 +5,6 @@

#include "artiq_personality.h"
#include "ad9154.h"
#include "ad9154_reg.h"

#ifdef CONFIG_AD9154_DAC_CS

@@ -44,7 +43,7 @@ void ad9154_write(uint16_t addr, uint8_t data)
uint8_t ad9154_read(uint16_t addr)
{
ad9154_xfer(AD9154_READ | addr, 0);
return ad9154_spi_data_read_read() & 0xff;
return ad9154_spi_data_read_read();
}

#endif
2 changes: 2 additions & 0 deletions artiq/runtime/ad9154.h
Original file line number Diff line number Diff line change
@@ -3,6 +3,8 @@

#ifdef CONFIG_AD9154_DAC_CS

#include "ad9154_reg.h"

void ad9154_spi_config(void);
void ad9154_write(uint16_t addr, uint8_t data);
uint8_t ad9154_read(uint16_t addr);
2 changes: 1 addition & 1 deletion artiq/runtime/ad9516.c
Original file line number Diff line number Diff line change
@@ -45,7 +45,7 @@ uint8_t ad9516_read(uint16_t addr)
ad9154_spi_xfer_len_write_write(16);
ad9154_spi_xfer_len_read_write(8);
ad9516_xfer(AD9516_READ | addr, 0);
return ad9154_spi_data_read_read() & 0xff;
return ad9154_spi_data_read_read();
}

#endif
2 changes: 2 additions & 0 deletions artiq/runtime/ad9516.h
Original file line number Diff line number Diff line change
@@ -3,6 +3,8 @@

#ifdef CONFIG_AD9154_CLK_CS

#include "ad9516_reg.h"

void ad9516_spi_config(void);
void ad9516_write(uint16_t addr, uint8_t data);
uint8_t ad9516_read(uint16_t addr);
2 changes: 1 addition & 1 deletion artiq/runtime/ad9516_reg.h
Original file line number Diff line number Diff line change
@@ -28,7 +28,7 @@
#define AD9516_A_COUNTER 0x013

#define AD9516_B_COUNTER_LSB 0x014
#define AD9516_B_COUNTER_LSB 0x015
#define AD9516_B_COUNTER_MSB 0x015

#define AD9516_PLL_CONTROL_1 0x016
#define AD9516_PRESCALER_P (1 << 0) /* 3, 0x06 R/W */
51 changes: 51 additions & 0 deletions artiq/runtime/test_mode.c
Original file line number Diff line number Diff line change
@@ -611,7 +611,58 @@ static void dac_test_xfer(char *addr, char *data)

static void clk_test(void)
{
uint32_t x;

ad9516_spi_config();

/* reset */
ad9516_write(AD9516_SERIAL_PORT_CONFIGURATION,
AD9516_SOFT_RESET | AD9516_SOFT_RESET_MIRRORED |
AD9516_LONG_INSTRUCTION | AD9516_LONG_INSTRUCTION_MIRRORED);
ad9516_write(AD9516_SERIAL_PORT_CONFIGURATION,
AD9516_LONG_INSTRUCTION | AD9516_LONG_INSTRUCTION_MIRRORED);
if (ad9516_read(AD9516_PART_ID) != 0x41) {
printf("not present\n");
return;
}

ad9516_write(AD9516_INPUT_CLKS, AD9516_SELECT_VCO_OR_CLK); /* VCO 2400 MHz */
ad9516_write(AD9516_VCO_DIVIDER, 0b011); /* 5, 480 MHz */

/* DAC deviceclk */
ad9516_write(AD9516_DIVIDER_0_1, 0); /* no bypass */
ad9516_write(AD9516_DIVIDER_0_0, 15*AD9516_DIVIDER_0_HIGH_CYCLES |
15*AD9516_DIVIDER_0_LOW_CYCLES); /* 15 MHz */
ad9516_write(AD9516_OUT1, 2*AD9516_OUT1_LVPECLDIFFERENTIAL_VOLTAGE);

/* sysref */
ad9516_write(AD9516_DIVIDER_3_3, AD9516_DIVIDER_3_BYPASS_2);
ad9516_write(AD9516_DIVIDER_3_0, 15*AD9516_DIVIDER_3_HIGH_CYCLES_1 |
15*AD9516_DIVIDER_3_LOW_CYCLES_1); /* 15 MHz */
ad9516_write(AD9516_OUT6, 1*AD9516_OUT6_LVDS_OUTPUT_CURRENT |
AD9516_OUT6_CMOS_OUTPUT_POLARITY);
ad9516_write(AD9516_OUT7, 1*AD9516_OUT7_LVDS_OUTPUT_CURRENT |
AD9516_OUT7_CMOS_OUTPUT_POLARITY);

ad9516_write(AD9516_DIVIDER_4_3, AD9516_DIVIDER_4_BYPASS_2);
ad9516_write(AD9516_DIVIDER_4_0, 15*AD9516_DIVIDER_4_HIGH_CYCLES_1 |
15*AD9516_DIVIDER_4_LOW_CYCLES_1); /* 15 MHz */
ad9516_write(AD9516_OUT9, 1*AD9516_OUT9_LVDS_OUTPUT_CURRENT |
AD9516_OUT9_CMOS_OUTPUT_POLARITY);

ad9516_write(AD9516_PLL_CONTROL_3, AD9516_VCO_CAL_NOW |
3*AD9516_VCO_CALIBRATION_DIVIDER);

ad9516_write(AD9516_UPDATE_ALL_REGISTERS, 1);

for(x=0; x<10000; x++) {
if (ad9516_read(AD9516_PLL_READBACK) & AD9516_VCO_CAL_FINISHED) {
printf("clk pass\n");
return;
}
}

printf("clk fail\n");
}

static void clk_test_xfer(char *addr, char *data)