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base repository: m-labs/artiq
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compare: 18d18b668569
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  • 3 commits
  • 5 files changed
  • 2 contributors

Commits on Oct 10, 2016

  1. ad9516: duty cycle correction

    jordens committed Oct 10, 2016
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    e27228f View commit details
  2. ttl_simple: add pure Input

    (no Tristate for internal signals)
    jordens committed Oct 10, 2016
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    f5f7acc View commit details
  3. Copy the full SHA
    18d18b6 View commit details
Showing with 65 additions and 13 deletions.
  1. +10 −4 artiq/examples/phaser/device_db.pyon
  2. +2 −2 artiq/examples/phaser/startup_kernel.py
  3. +37 −0 artiq/gateware/rtio/phy/ttl_simple.py
  4. +13 −6 artiq/gateware/targets/kc705.py
  5. +3 −1 doc/manual/core_device.rst
14 changes: 10 additions & 4 deletions artiq/examples/phaser/device_db.pyon
Original file line number Diff line number Diff line change
@@ -44,28 +44,34 @@
"class": "TTLInOut",
"arguments": {"channel": 2}
},
"sync": {
"type": "local",
"module": "artiq.coredevice.ttl",
"class": "TTLInOut",
"arguments": {"channel": 3}
},
"sawg0": {
"type": "local",
"module": "artiq.coredevice.sawg",
"class": "SAWG",
"arguments": {"channel_base": 3, "parallelism": 4}
"arguments": {"channel_base": 4, "parallelism": 4}
},
"sawg1": {
"type": "local",
"module": "artiq.coredevice.sawg",
"class": "SAWG",
"arguments": {"channel_base": 6, "parallelism": 4}
"arguments": {"channel_base": 7, "parallelism": 4}
},
"sawg2": {
"type": "local",
"module": "artiq.coredevice.sawg",
"class": "SAWG",
"arguments": {"channel_base": 9, "parallelism": 4}
"arguments": {"channel_base": 10, "parallelism": 4}
},
"sawg3": {
"type": "local",
"module": "artiq.coredevice.sawg",
"class": "SAWG",
"arguments": {"channel_base": 12, "parallelism": 4}
"arguments": {"channel_base": 13, "parallelism": 4}
}
}
4 changes: 2 additions & 2 deletions artiq/examples/phaser/startup_kernel.py
Original file line number Diff line number Diff line change
@@ -52,7 +52,7 @@ def clock_setup(self):
self.ad9154.clock_write(AD9516_DIVIDER_4_0,
(4//2-1)*AD9516_DIVIDER_0_HIGH_CYCLES |
(4//2-1)*AD9516_DIVIDER_0_LOW_CYCLES)
self.ad9154.clock_write(AD9516_DIVIDER_4_4, 1*AD9516_DIVIDER_4_DCCOFF)
self.ad9154.clock_write(AD9516_DIVIDER_4_4, 0*AD9516_DIVIDER_4_DCCOFF)
self.ad9154.clock_write(AD9516_OUT9, 1*AD9516_OUT9_LVDS_OUTPUT_CURRENT |
2*AD9516_OUT9_LVDS_CMOS_OUTPUT_POLARITY |
0*AD9516_OUT9_SELECT_LVDS_CMOS)
@@ -66,7 +66,7 @@ def clock_setup(self):
(2//2-1)*AD9516_DIVIDER_3_LOW_CYCLES_2)
self.ad9154.clock_write(AD9516_DIVIDER_3_3, 0*AD9516_DIVIDER_3_NOSYNC |
0*AD9516_DIVIDER_3_BYPASS_1 | 0*AD9516_DIVIDER_3_BYPASS_2)
self.ad9154.clock_write(AD9516_DIVIDER_3_4, 1*AD9516_DIVIDER_3_DCCOFF)
self.ad9154.clock_write(AD9516_DIVIDER_3_4, 0*AD9516_DIVIDER_3_DCCOFF)
self.ad9154.clock_write(AD9516_OUT6, 1*AD9516_OUT6_LVDS_OUTPUT_CURRENT |
2*AD9516_OUT6_LVDS_CMOS_OUTPUT_POLARITY |
0*AD9516_OUT6_SELECT_LVDS_CMOS)
37 changes: 37 additions & 0 deletions artiq/gateware/rtio/phy/ttl_simple.py
Original file line number Diff line number Diff line change
@@ -27,6 +27,43 @@ def __init__(self, pad):
]


class Input(Module):
def __init__(self, pad):
self.rtlink = rtlink.Interface(
rtlink.OInterface(2, 2),
rtlink.IInterface(1))
self.overrides = []
self.probes = []

# # #

sensitivity = Signal(2)

sample = Signal()
self.sync.rio += [
sample.eq(0),
If(self.rtlink.o.stb & self.rtlink.o.address[1],
sensitivity.eq(self.rtlink.o.data),
If(self.rtlink.o.address[0], sample.eq(1))
)
]

i = Signal()
i_d = Signal()
self.specials += MultiReg(pad, i, "rio_phy")
self.sync.rio_phy += i_d.eq(i)
self.comb += [
self.rtlink.i.stb.eq(
sample |
(sensitivity[0] & ( i & ~i_d)) |
(sensitivity[1] & (~i & i_d))
),
self.rtlink.i.data.eq(i)
]

self.probes += [i]


class Inout(Module):
def __init__(self, pad):
self.rtlink = rtlink.Interface(
19 changes: 13 additions & 6 deletions artiq/gateware/targets/kc705.py
Original file line number Diff line number Diff line change
@@ -149,8 +149,10 @@ def __init__(self, cpu_type="or1k", **kwargs):
self.register_kernel_cpu_csrdevice("i2c")
self.config["I2C_BUS_COUNT"] = 1

def add_rtio(self, rtio_channels, crg=_RTIOCRG):
self.submodules.rtio_crg = crg(self.platform, self.crg.cd_sys.clk)
def add_rtio(self, rtio_channels, rtio_crg=None):
if rtio_crg is None:
rtio_crg = _RTIOCRG(self.platform, self.crg.cd_sys.clk)
self.submodules.rtio_crg = rtio_crg
self.csr_devices.append("rtio_crg")
self.submodules.rtio = rtio.RTIO(rtio_channels)
self.register_kernel_cpu_csrdevice("rtio")
@@ -454,6 +456,7 @@ def __init__(self, platform, rtio_crg):
jesd_sync = Signal()
self.specials += DifferentialInput(
sync_pads.p, sync_pads.n, jesd_sync)
self.jesd_sync = jesd_sync

ps = JESD204BPhysicalSettings(l=4, m=4, n=16, np=16)
ts = JESD204BTransportSettings(f=2, s=1, k=16, cs=1)
@@ -510,6 +513,12 @@ def __init__(self, cpu_type="or1k", **kwargs):
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=32,
ofifo_depth=2))

jesd_sync = Signal()
phy = ttl_simple.Input(jesd_sync)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=32,
ofifo_depth=2))

self.config["RTIO_REGULAR_TTL_COUNT"] = len(rtio_channels)

self.config["RTIO_FIRST_SAWG_CHANNEL"] = len(rtio_channels)
@@ -522,11 +531,8 @@ def __init__(self, cpu_type="or1k", **kwargs):

self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
rtio_channels.append(rtio.LogChannel())
self.add_rtio(rtio_channels, _PhaserCRG)
self.add_rtio(rtio_channels, _PhaserCRG(platform, self.crg.cd_sys.clk))

# jesd_sysref = Signal()
# self.specials += DifferentialInput(
# sysref_pads.p, sysref_pads.n, jesd_sysref)
to_rtio = ClockDomainsRenamer({"sys": "rtio"})
self.submodules.ad9154 = to_rtio(AD9154(platform, self.rtio_crg))
self.register_kernel_cpu_csrdevice("ad9154")
@@ -537,6 +543,7 @@ def __init__(self, cpu_type="or1k", **kwargs):
"converter{}".format(i))
# while at 5 GBps, take every second sample... FIXME
self.comb += conv.eq(Cat(ch.o[::2]))
self.comb += jesd_sync.eq(self.ad9154.jesd_sync)


def main():
4 changes: 3 additions & 1 deletion doc/manual/core_device.rst
Original file line number Diff line number Diff line change
@@ -170,8 +170,10 @@ The Phaser adapter is an AD9154-FMC-EBZ, a 4 channel 2.4 GHz DAC on an FMC HPC c
+--------------+------------+--------------+
| 2 | SYSREF | Input |
+--------------+------------+--------------+
| 3 | SYNC | Input |
+--------------+------------+--------------+

The SAWG channels start with RTIO channel number 3, each occupying 3 channels.
The SAWG channels start with RTIO channel number 4, each occupying 3 channels.

The board has one non-RTIO SPI bus that is accessible through
:mod:`artiq.coredevice.ad9154`.