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csr: simulation access methods
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sbourdeauducq committed Oct 24, 2016
1 parent 9f471a1 commit 3e52b91
Showing 1 changed file with 24 additions and 0 deletions.
24 changes: 24 additions & 0 deletions misoc/interconnect/csr.py
Original file line number Diff line number Diff line change
@@ -20,6 +20,9 @@ def __init__(self, value, bits_sign=None, name=None):
if self.name is None:
raise ValueError("Cannot extract CSR name from code, need to specify.")

def read(self):
return self.value.value


class CSR(_CSRBase):
def __init__(self, size=1, name=None):
@@ -28,6 +31,15 @@ def __init__(self, size=1, name=None):
self.r = Signal(self.size, name=self.name + "_r")
self.w = Signal(self.size, name=self.name + "_w")

def read(self):
return (yield self.w)

def write(self, value):
yield self.r.eq(value)
yield self.re.eq(1)
yield
yield self.re.eq(0)


class _CompoundCSR(_CSRBase, Module):
def __init__(self, size, name):
@@ -56,6 +68,9 @@ def do_finalize(self, busword):
self.comb += sc.w.eq(self.status[i*busword:i*busword+nbits])
self.simple_csrs.append(sc)

def read(self):
return (yield self.status)


class CSRStorage(_CompoundCSR):
def __init__(self, size=1, reset=0, atomic_write=False, write_from_dev=False, alignment_bits=0, name=None):
@@ -99,6 +114,15 @@ def do_finalize(self, busword):
self.sync += If(sc.re, self.storage_full[lo:hi].eq(sc.r))
self.sync += self.re.eq(sc.re)

def read(self):
return (yield self.storage) << self.alignment_bits

def write(self, value):
yield self.storage.eq(value >> self.alignment_bits)
yield self.re.eq(1)
yield
yield self.re.eq(0)


def csrprefix(prefix, csrs, done):
for csr in csrs:

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