Skip to content
Permalink

Comparing changes

Choose two branches to see what’s changed or to start a new pull request. If you need to, you can also or learn more about diff comparisons.

Open a pull request

Create a new pull request by comparing changes across two branches. If you need to, you can also . Learn more about diff comparisons here.
base repository: m-labs/artiq
Failed to load repositories. Confirm that selected base ref is valid, then try again.
Loading
base: 72932fccec81
Choose a base ref
...
head repository: m-labs/artiq
Failed to load repositories. Confirm that selected head ref is valid, then try again.
Loading
compare: 1f9365872483
Choose a head ref
  • 4 commits
  • 4 files changed
  • 2 contributors

Commits on Oct 7, 2016

  1. ad9514_status: more info

    jordens committed Oct 7, 2016
    Copy the full SHA
    1157a3a View commit details
  2. phaser: tweak sawg example

    jordens committed Oct 7, 2016
    Copy the full SHA
    4e60a6a View commit details
  3. Copy the full SHA
    89a30b6 View commit details
  4. Copy the full SHA
    1f93658 View commit details
75 changes: 59 additions & 16 deletions artiq/examples/phaser/repository/dac_setup.py
Original file line number Diff line number Diff line change
@@ -33,11 +33,11 @@ def build(self):

@kernel
def run(self):
self.core.reset()
self.core.break_realtime()
self.ad9154.jesd_enable(0)
self.ad9154.jesd_prbs(0)
self.ad9154.init()
self.dac_setup()
self.ad9154.jesd_prbs(0)
self.busywait_us(200000)
self.ad9154.jesd_enable(1)
while not self.ad9154.jesd_ready():
@@ -60,7 +60,7 @@ def dac_setup(self):
self.busywait_us(100)
if ((self.ad9154.dac_read(AD9154_PRODIDH) << 8) |
self.ad9154.dac_read(AD9154_PRODIDL) != 0x9154):
return
raise ValueError("AD9154 not found")

self.ad9154.dac_write(AD9154_PWRCNTRL0,
AD9154_PD_DAC0_SET(0) | AD9154_PD_DAC1_SET(0) |
@@ -80,13 +80,6 @@ def dac_setup(self):
AD9154_HYS_CNTRL1_SET(0) | AD9154_SYSREF_RISE_SET(0) |
AD9154_HYS_ON_SET(0) | AD9154_PD_SYSREF_BUFFER_SET(0))

self.ad9154.dac_write(AD9154_IRQEN_STATUSMODE0,
AD9154_IRQEN_SMODE_LANEFIFOERR_SET(1) |
AD9154_IRQEN_SMODE_SERPLLLOCK_SET(1) |
AD9154_IRQEN_SMODE_SERPLLLOST_SET(1) |
AD9154_IRQEN_SMODE_DACPLLLOCK_SET(1) |
AD9154_IRQEN_SMODE_DACPLLLOST_SET(1))

self.ad9154.dac_write(AD9154_DEVICE_CONFIG_REG_0, 0x8b) # magic
self.ad9154.dac_write(AD9154_DEVICE_CONFIG_REG_1, 0x01) # magic
self.ad9154.dac_write(AD9154_DEVICE_CONFIG_REG_2, 0x01) # magic
@@ -258,14 +251,21 @@ def dac_setup(self):
self.ad9154.dac_write(AD9154_LMFC_VAR_1, 0x0a)
self.ad9154.dac_write(AD9154_SYNC_ERRWINDOW, 0) # +- 1/2 DAC clock
self.ad9154.dac_write(AD9154_SYNC_CONTROL,
AD9154_SYNCMODE_SET(1) | AD9154_SYNCENABLE_SET(0) |
AD9154_SYNCARM_SET(0))
AD9154_SYNCMODE_SET(0x9) | AD9154_SYNCENABLE_SET(0) |
AD9154_SYNCARM_SET(0) | AD9154_SYNCCLRSTKY_SET(1) |
AD9154_SYNCCLRLAST_SET(1))
self.ad9154.dac_write(AD9154_SYNC_CONTROL,
AD9154_SYNCMODE_SET(1) | AD9154_SYNCENABLE_SET(1) |
AD9154_SYNCARM_SET(0))
AD9154_SYNCMODE_SET(0x9) | AD9154_SYNCENABLE_SET(1) |
AD9154_SYNCARM_SET(0) | AD9154_SYNCCLRSTKY_SET(1) |
AD9154_SYNCCLRLAST_SET(1))
self.ad9154.dac_write(AD9154_SYNC_CONTROL,
AD9154_SYNCMODE_SET(1) | AD9154_SYNCENABLE_SET(1) |
AD9154_SYNCARM_SET(1))
AD9154_SYNCMODE_SET(0x9) | AD9154_SYNCENABLE_SET(1) |
AD9154_SYNCARM_SET(1) | AD9154_SYNCCLRSTKY_SET(0) |
AD9154_SYNCCLRLAST_SET(0))
self.busywait_us(1000) # ensure at leas one sysref edge
if not AD9154_SYNC_LOCK_GET(self.ad9154.dac_read(AD9154_SYNC_STATUS)):
pass
# raise ValueError("no sync lock")
self.ad9154.dac_write(AD9154_XBAR_LN_0_1,
AD9154_LOGICAL_LANE0_SRC_SET(7) | AD9154_LOGICAL_LANE1_SRC_SET(6))
self.ad9154.dac_write(AD9154_XBAR_LN_2_3,
@@ -278,3 +278,46 @@ def dac_setup(self):
self.ad9154.dac_write(AD9154_GENERAL_JRX_CTRL_0,
AD9154_LINK_EN_SET(0x1) | AD9154_LINK_PAGE_SET(0) |
AD9154_LINK_MODE_SET(0) | AD9154_CHECKSUM_MODE_SET(0))

self.busywait_us(1000)

self.ad9154.dac_write(AD9154_IRQ_STATUS0, 0x00)
self.ad9154.dac_write(AD9154_IRQ_STATUS1, 0x00)
self.ad9154.dac_write(AD9154_IRQ_STATUS2, 0x00)
self.ad9154.dac_write(AD9154_IRQ_STATUS3, 0x00)

self.ad9154.dac_write(AD9154_IRQEN_STATUSMODE0,
AD9154_IRQEN_SMODE_LANEFIFOERR_SET(1) |
AD9154_IRQEN_SMODE_SERPLLLOCK_SET(1) |
AD9154_IRQEN_SMODE_SERPLLLOST_SET(1) |
AD9154_IRQEN_SMODE_DACPLLLOCK_SET(1) |
AD9154_IRQEN_SMODE_DACPLLLOST_SET(1))

self.ad9154.dac_write(AD9154_IRQEN_STATUSMODE1,
AD9154_IRQEN_SMODE_PRBS0_SET(1) |
AD9154_IRQEN_SMODE_PRBS1_SET(1) |
AD9154_IRQEN_SMODE_PRBS2_SET(1) |
AD9154_IRQEN_SMODE_PRBS3_SET(1))

self.ad9154.dac_write(AD9154_IRQEN_STATUSMODE2,
AD9154_IRQEN_SMODE_SYNC_TRIP0_SET(1) |
AD9154_IRQEN_SMODE_SYNC_WLIM0_SET(1) |
AD9154_IRQEN_SMODE_SYNC_ROTATE0_SET(1) |
AD9154_IRQEN_SMODE_SYNC_LOCK0_SET(1) |
AD9154_IRQEN_SMODE_NCO_ALIGN0_SET(1) |
AD9154_IRQEN_SMODE_BLNKDONE0_SET(1) |
AD9154_IRQEN_SMODE_PDPERR0_SET(1))

self.ad9154.dac_write(AD9154_IRQEN_STATUSMODE3,
AD9154_IRQEN_SMODE_SYNC_TRIP1_SET(1) |
AD9154_IRQEN_SMODE_SYNC_WLIM1_SET(1) |
AD9154_IRQEN_SMODE_SYNC_ROTATE1_SET(1) |
AD9154_IRQEN_SMODE_SYNC_LOCK1_SET(1) |
AD9154_IRQEN_SMODE_NCO_ALIGN1_SET(1) |
AD9154_IRQEN_SMODE_BLNKDONE1_SET(1) |
AD9154_IRQEN_SMODE_PDPERR1_SET(1))

self.ad9154.dac_write(AD9154_IRQ_STATUS0, 0x00)
self.ad9154.dac_write(AD9154_IRQ_STATUS1, 0x00)
self.ad9154.dac_write(AD9154_IRQ_STATUS2, 0x00)
self.ad9154.dac_write(AD9154_IRQ_STATUS3, 0x00)
12 changes: 6 additions & 6 deletions artiq/examples/phaser/repository/sawg.py
Original file line number Diff line number Diff line change
@@ -13,17 +13,17 @@ def build(self):

@kernel
def run(self):
self.core.reset()

self.core.break_realtime()
delay(100*us)

self.sawg0.set_amplitude(.1)
self.sawg1.set_amplitude(-1.)
self.sawg1.set_amplitude(-.9)
self.sawg2.set_amplitude(.5)
self.sawg3.set_amplitude(.5)
self.sawg0.set_frequency(1*MHz)
self.sawg1.set_frequency(100*MHz)
self.sawg2.set_frequency(200*MHz)
self.sawg3.set_frequency(200*MHz)
self.sawg1.set_frequency(10*MHz)
self.sawg2.set_frequency(20*MHz)
self.sawg3.set_frequency(20*MHz)
self.sawg0.set_phase(0.)
self.sawg1.set_phase(0.)
self.sawg2.set_phase(0.)
9 changes: 9 additions & 0 deletions artiq/examples/phaser/repository/test_ad9154_status.py
Original file line number Diff line number Diff line change
@@ -80,6 +80,11 @@ def print_status(self):
self.p("GOODCHECKSUM: 0x%02x", self.ad9154.dac_read(AD9154_GOODCHKSUMFLG))
self.p("INITIALLANESYNC: 0x%02x", self.ad9154.dac_read(AD9154_INITLANESYNCFLG))

x = self.ad9154.dac_read(AD9154_SYNC_CURRERR_H)
self.p("SYNC_CURRERR: 0x%04x", self.ad9154.dac_read(AD9154_SYNC_CURRERR_L) |
(AD9154_CURRERROR_H_GET(x) << 8))
self.p("SYNC_CURROVER: %d, SYNC_CURRUNDER: %d",
AD9154_CURROVER_GET(x), AD9154_CURRUNDER_GET(x))
x = self.ad9154.dac_read(AD9154_SYNC_LASTERR_H)
self.p("SYNC_LASTERR: 0x%04x", self.ad9154.dac_read(AD9154_SYNC_LASTERR_L) |
(AD9154_LASTERROR_H_GET(x) << 8))
@@ -124,3 +129,7 @@ def print_status(self):
self.p("BADDISPARITY: 0x%02x", self.ad9154.dac_read(AD9154_BADDISPARITY))
self.p("NITDISPARITY: 0x%02x", self.ad9154.dac_read(AD9154_NIT_W))
self.p("UNEXPECTEDCONTROL: 0x%02x", self.ad9154.dac_read(AD9154_UNEXPECTEDCONTROL_W))
self.p("DYN_LINK_LATENCY_0: 0x%02x",
self.ad9154.dac_read(AD9154_DYN_LINK_LATENCY_0))
self.p("DYN_LINK_LATENCY_1: 0x%02x",
self.ad9154.dac_read(AD9154_DYN_LINK_LATENCY_1))
2 changes: 1 addition & 1 deletion artiq/examples/phaser/startup_kernel.py
Original file line number Diff line number Diff line change
@@ -26,7 +26,7 @@ def clock_setup(self):
AD9516_LONG_INSTRUCTION | AD9516_LONG_INSTRUCTION_MIRRORED |
AD9516_SDO_ACTIVE | AD9516_SDO_ACTIVE_MIRRORED)
if self.ad9154.clock_read(AD9516_PART_ID) != 0x41:
return
raise ValueError("AD9516 not found")

# use clk input, dclk=clk/4
self.ad9154.clock_write(AD9516_PFD_AND_CHARGE_PUMP, 1*AD9516_PLL_POWER_DOWN |