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base repository: azonenberg/openfpga
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head repository: azonenberg/openfpga
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compare: ab4190091ab9
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  • 4 commits
  • 2 files changed
  • 1 contributor

Commits on Oct 15, 2016

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Showing with 33 additions and 9 deletions.
  1. +1 −1 src/gp4par/gp4par.h
  2. +32 −8 src/gp4par/par_main.cpp
2 changes: 1 addition & 1 deletion src/gp4par/gp4par.h
Original file line number Diff line number Diff line change
@@ -53,7 +53,7 @@ void ApplyLocConstraints(Greenpak4Netlist* netlist, PARGraph* ngraph, PARGraph*
bool DoPAR(Greenpak4Netlist* netlist, Greenpak4Device* device);

//DRC
void PostPARDRC(PARGraph* netlist, Greenpak4Device* device);
bool PostPARDRC(PARGraph* netlist, Greenpak4Device* device);

//Committing
bool CommitChanges(PARGraph* device, Greenpak4Device* pdev, unsigned int* num_routes_used);
40 changes: 32 additions & 8 deletions src/gp4par/par_main.cpp
Original file line number Diff line number Diff line change
@@ -59,7 +59,8 @@ bool DoPAR(Greenpak4Netlist* netlist, Greenpak4Device* device)
}

//Final DRC to make sure the placement is sane
PostPARDRC(ngraph, device);
if(!PostPARDRC(ngraph, device))
return false;

//Print reports
PrintUtilizationReport(ngraph, device, num_routes_used);
@@ -74,11 +75,13 @@ bool DoPAR(Greenpak4Netlist* netlist, Greenpak4Device* device)
/**
@brief Do various sanity checks after the design is routed
*/
void PostPARDRC(PARGraph* netlist, Greenpak4Device* device)
bool PostPARDRC(PARGraph* netlist, Greenpak4Device* device)
{
LogNotice("\nChecking post-route design rules...\n");
LogIndenter li;

bool ok = true;

//Check for nodes in the netlist that have no load
for(uint32_t i=0; i<netlist->GetNumNodes(); i++)
{
@@ -93,7 +96,7 @@ void PostPARDRC(PARGraph* netlist, Greenpak4Device* device)
LogError(
"Node \"%s\" is not mapped to any site in the device\n",
src->m_name.c_str());
exit(-1);
ok = false;
}

//Do not warn if power rails have no load, that's perfectly normal
@@ -141,7 +144,7 @@ void PostPARDRC(PARGraph* netlist, Greenpak4Device* device)
it->first,
signal.GetOutputName().c_str()
);
exit(-1);
ok = false;
}
}
}
@@ -223,16 +226,18 @@ void PostPARDRC(PARGraph* netlist, Greenpak4Device* device)
LogError(
"Multiple comparators tried to simultaneously use different outputs from "
"the ACMP0 input mux\n");
LogIndenter li;
for(auto p : inputs)
{
LogNotice(" Comparator %10s requested %s\n",
LogNotice("Comparator %10s requested %s\n",
p.first.c_str(), p.second.GetOutputName().c_str());
}
exit(-1);
ok = false;
}

//If ACMP0 is not used, but we use its output, configure it
//TODO: for better power efficiency, turn on only when a downstream comparator is on?
//TODO: This really should not be done in the DRC
if( (device->GetAcmp(0)->GetInput() == gnd) && (inputs.size() > 0) )
{
LogNotice(
@@ -279,13 +284,32 @@ void PostPARDRC(PARGraph* netlist, Greenpak4Device* device)
"Multiple oscillators have power-down enabled, but do not share the same power-down signal\n");
for(auto p : powerdowns)
LogNotice(" Oscillator %10s powerdown is %s\n", p.first.c_str(), p.second.GetOutputName().c_str());
exit(-1);
ok = false;
}
}

//If the PGA is used, we cannot use DAC1 (undocumented conflict, datasheet says nothing about this...)
//It appears that enabling the PGA turns on the ADC and causes DAC1 to emit a sawtooth waveform, regardless
//of whether there is any actual use of the ADC subsystem.
if(device->GetPart() == Greenpak4Device::GREENPAK4_SLG46620)
{
auto dac1 = device->GetDAC(1);

if(pga->IsUsed() && dac1->IsUsed())
{
LogError(
"Both DAC1 and the PGA are used. This is illegal due to a poorly documented control hazard.\n"
"Enabling the PGA turns on the SAR ADC, forcing DAC1 to emit a sawtooth waveform instead of the "
"desired signal.\n");
ok = false;
}
}

//TODO: Cannot use DAC1 when PGA is used either (undocumented conflict, datasheet says nothing about this)
//TODO: Cannot use DAC1 when ADC is used
//TODO: Cannot use DAC0 when ADC/PGA pseudo-diff mode is used

//Done
return ok;
}

void CheckAnalogIbuf(Greenpak4BitstreamEntity* load, Greenpak4IOB* iob)