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base repository: m-labs/migen
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compare: e152de3657fa
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  • 3 commits
  • 3 files changed
  • 1 contributor

Commits on Oct 21, 2016

  1. doc: explain how to get a VCD dump from simulator.

    whitequark committed Oct 21, 2016
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    20a8dd3 View commit details
  2. doc: expand on the Replicate FHDL section.

    whitequark committed Oct 21, 2016
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    7403950 View commit details
  3. fhdl: translate the % operator too.

    whitequark committed Oct 21, 2016
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    e152de3 View commit details
Showing with 16 additions and 2 deletions.
  1. +7 −0 doc/fhdl.rst
  2. +4 −1 doc/simulation.rst
  3. +5 −1 migen/fhdl/structure.py
7 changes: 7 additions & 0 deletions doc/fhdl.rst
Original file line number Diff line number Diff line change
@@ -74,6 +74,13 @@ Replications
============

The ``Replicate`` object represents the equivalent of {count{expression}} in Verilog.
For example, the expression: ::

Replicate(0, 4)

is equivalent to::

Cat(0, 0, 0, 0)

Statements
**********
5 changes: 4 additions & 1 deletion doc/simulation.rst
Original file line number Diff line number Diff line change
@@ -10,7 +10,10 @@ Migen lets you write testbenches using Python's generator functions. Such testbe
#. Clocking: simulation can be advanced by one clock cycle using ``yield``;
#. Composition: control can be transferred to another testbench function using ``yield from run_other()``.

A testbench can be run using the ``run_simulation`` function from ``migen.sim``; ``run_simulation(mod, bench)`` runs the generator function ``bench`` against the logic defined in an FHDL module ``mod``.
A testbench can be run using the ``run_simulation`` function from ``migen.sim``; ``run_simulation(dut, bench)`` runs the generator function ``bench`` against the logic defined in an FHDL module ``dut``.

Passing the ``vcd_name="file.vcd"`` argument to ``run_simulation`` will cause it to write a VCD
dump of the signals inside ``dut`` to ``file.vcd``.

Examples
********
6 changes: 5 additions & 1 deletion migen/fhdl/structure.py
Original file line number Diff line number Diff line change
@@ -55,6 +55,10 @@ def __mul__(self, other):
return _Operator("*", [self, other])
def __rmul__(self, other):
return _Operator("*", [other, self])
def __mod__(self, other):
return _Operator("%", [self, other])
def __rmod__(self, other):
return _Operator("%", [other, self])
def __lshift__(self, other):
return _Operator("<<<", [self, other])
def __rlshift__(self, other):
@@ -525,7 +529,7 @@ def __init__(self, test, cases):
for k, v in cases.items():
if isinstance(k, (bool, int)):
k = Constant(k)
if (not isinstance(k, Constant)
if (not isinstance(k, Constant)
and not (isinstance(k, str) and k == "default")):
raise TypeError("Case object is not a Migen constant")
if not isinstance(v, _collections.Iterable):