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  • 3 commits
  • 4 files changed
  • 1 contributor

Commits on Oct 12, 2016

  1. Revert "phaser: 500 MHz dacclock"

    This reverts commit 5f737be.
    jordens committed Oct 12, 2016
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    2d14864 View commit details
  2. phaser: tweak sawg example

    jordens committed Oct 12, 2016
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    0d1ed24 View commit details
  3. phaser: update README

    jordens committed Oct 12, 2016
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    9880b1e View commit details
Showing with 50 additions and 60 deletions.
  1. +35 −40 README_PHASER.rst
  2. +4 −4 artiq/examples/phaser/repository/dac_setup.py
  3. +7 −8 artiq/examples/phaser/repository/sawg.py
  4. +4 −8 artiq/examples/phaser/startup_kernel.py
75 changes: 35 additions & 40 deletions README_PHASER.rst
Original file line number Diff line number Diff line change
@@ -3,51 +3,38 @@ ARTIQ Phaser

This ARTIQ branch contains a proof-of-concept design of a GHz-datarate multichannel direct digital synthesizer (DDS) compatible with ARTIQ's RTIO channels.
In later developments this proof-of-concept can be expanded to provide a two-tone output with spline modulation and multi-DAC synchronization.
Ultimately it will be the basis for the ARTIQ Sayma project. See https://github.com/m-labs/sayma and https://github.com/m-labs/artiq-hardware
Ultimately it will be the basis for the ARTIQ Sayma Smart Arbitrary Waveform Generator project. See https://github.com/m-labs/sayma and https://github.com/m-labs/artiq-hardware.

The hardware required is a KC705 with an AD9154-FMC-EBZ plugged into the HPC connector and a low-jitter 2 GHz reference clock.

Features:
*Features*:

* 4 channels
* 500 MHz data rate per channel (KC705 limitation)
* 4x interpolation to 2 GHz DAC sample rate
* Real-time control over amplitude, frequency, phase through ARTIQ RTIO
channels
* Full configurability of the AD9154 and AD9516 through SPI with ARTIQ kernel
support
* Real-time control over amplitude, frequency, phase of each channel through ARTIQ RTIO commands
* Full configurability of the AD9154 and AD9516 through SPI with ARTIQ kernel support
* All SPI registers and register bits exposed as human readable names
* Parametrized JESD204B core (also capable of operation with eight lanes)
* The code can be reconfigured, e.g. to support 2 channels at 1 GHz datarate or to support 4 channels at 300 MHz data rate, no interpolation, and using mix mode to stress the second and third Nyquist zones (150-300 MHz and 300-450 MHz).
* The code can be reconfigured. Possible example configurations are: support 2 channels at 1 GHz datarate, support 4 channels at 300 MHz data rate, no interpolation, and using mix mode to stress the second and third Nyquist zones (150-300 MHz and 300-450 MHz).

The hardware required to use the ARTIQ phaser branch is a KC705 with an AD9154-FMC-EBZ plugged into the HPC connector and a low-noise 2 GHz reference clock.

This work was supported by the Army Research Lab.

The additions and modifications to ARTIQ that were implemented for this project are:
The code that was developed for this project is located in several repositories:

* In ARTIQ, the SAWG and Phaser code: https://github.com/m-labs/artiq/compare/phaser
* The CORDIC core has been reused from the PDQ2 gateware
https://github.com/m-labs/pdq2
* The CORDIC core has been reused from the PDQ2 gateware https://github.com/m-labs/pdq2
* The Migen/MiSoC JESD204B core: https://github.com/m-labs/jesd204b


Installation
------------

These installation instructions are a short form of those in the ARTIQ manual.
Please refer to the manual for more details:
Please refer to and follow the ARTIQ manual for more details:
https://m-labs.hk/artiq/manual-release-2/index.html

* Set up a new conda environment and activate it.
* Checkout the ARTIQ phaser branch and the JESD204B core: ::

mkdir ~/src
cd ~/src
git clone --recursive -b phaser https://github.com/m-labs/artiq.git
git clone https://github.com/m-labs/jesd204b.git
cd jesd204b
python setup.py develop
cd ../artiq

* Install the standard ARTIQ runtime/install dependencies.
See ``conda/artiq/meta.yaml`` for a list.
They are all packaged as conda packages in ``m-labs/main``.
@@ -60,17 +47,26 @@ https://m-labs.hk/artiq/manual-release-2/index.html
- llvm-or1k
- rust-core-or1k
- cargo
- binutils-or1k-linux >=2.27
- binutils-or1k-linux

* Vivado
* Install a recent version of Vivado (tested and developed with 2016.2).
* Checkout the ARTIQ phaser branch and the JESD204B core: ::

Follow the ARTIQ manual's chapter on installing.
mkdir ~/src
cd ~/src
git clone --recursive -b phaser https://github.com/m-labs/artiq.git
git clone https://github.com/m-labs/jesd204b.git
cd jesd204b
python setup.py develop
cd ../artiq
python setup.py develop


Setup
-----

* Setup the KC705 (VADJ, jumpers, etc.) observing the ARTIQ manual.
* Setup the KC705 (jumpers, etc.) observing the ARTIQ manual.
VADJ does not need to be changed.
* On the AD9154-FMC-EBZ put jumpers:

- on XP1, between pin 5 and 6 (will keep the PIC in reset)
@@ -80,17 +76,17 @@ Setup

python -m artiq.gateware.targets.kc705 -H phaser --toolchain vivado

* Run the following OpenOCD commands to flash the ARTIQ transmitter design: ::
* Run the following OpenOCD command to flash the ARTIQ transmitter design: ::

openocd -f board/kc705.cfg -c "init; jtagspi_init 0 bscan_spi_xc7k325t.bit; jtagspi_program misoc_phaser_kc705/gateware/top.bin 0x000000; jtagspi_program misoc_phaser_kc705/software/bios/bios.bin 0xaf0000; jtagspi_program misoc_phaser_kc705/software/runtime/runtime.fbi 0xb00000; xc7_program xc7.tap; exit"

The proxy bitstream ``bscan_spi_xc7k325t.bit`` can be found at https://github.com/jordens/bscan_spi_bitstreams or in any ARTIQ conda package for the KC705.
See the source code of ``artiq_flash.py`` from ARTIQ for more details.

init
jtagspi_init 0 bscan_spi_xc7k325t.bit
jtagspi_program misoc_phaser_kc705/gateware/top.bin 0x000000
jtagspi_program misoc_phaser_kc705/software/bios/bios.bin 0xaf0000
jtagspi_program misoc_phaser_kc705/software/runtime/runtime.fbi 0xb00000
xc7_program xc7.tap
exit
If you are using the OpenOCD Conda package:

The proxy bitstream ``bscan_spi_xc7k325t.bit`` can be found at https://github.com/jordens/bscan_spi_bitstreams or in any ARTIQ conda package for the KC705. See the source code of ``artiq_flash.py`` from ARTIQ for more details.
* locate the OpenOCD scripts directory with: ``python3 -c "import artiq.frontend.artiq_flash as af; print(af.scripts_path)"``
* add ``-s <scripts directory>`` to the OpenOCD command line.

* Refer to the ARTIQ documentation to configure an IP address and other settings for the transmitter device.
If the board was running stock ARTIQ before, the settings will be kept.
@@ -103,12 +99,11 @@ Usage
-----

* An example device database, several status and test scripts are provided in ``artiq/examples/phaser/``.
* After each boot, run the ``dac_setup.py`` experiment to establish and align the data link (``artiq_run repository/dac_setup.py``).
* run ``artiq_run repository/sawg.py`` for an example that sets up amplitudes, frequencies,
and phases on all four DDS channels.
* After each boot, run the ``dac_setup.py`` experiment to establish the JESD204B links (``artiq_run repository/dac_setup.py``).
* Run ``artiq_run repository/sawg.py`` for an example that sets up amplitudes, frequencies, and phases on all four DDS channels.
* Implement your own experiments using the SAWG channels.
* Verify clock stability between the 2 GHz reference clock and the DAC outputs.
* Verify phase alignment between the DAC channels.
* Changes to the AD9154 configuration can also be performed at runtime in experiments.
See the example ``startup_kernel.py``.
See the example ``dac_setup.py``.
This can e.g. be used to enable and evaluate mix mode without having to change any other code (bitstream/bios/runtime/startup_kernel).
8 changes: 4 additions & 4 deletions artiq/examples/phaser/repository/dac_setup.py
Original file line number Diff line number Diff line change
@@ -20,9 +20,9 @@
jesd_settings = JESD204BSettings(ps, ts, did=0x5a, bid=0x5)
jesd_checksum = jesd_settings.get_configuration_checksum()
# external clk=2000MHz
# pclock=125MHz
# deviceclock_fpga=125MHz
# deviceclock_dac=500MHz
# pclock=250MHz
# deviceclock_fpga=500MHz
# deviceclock_dac=2000MHz


class DACSetup(EnvExperiment):
@@ -100,7 +100,7 @@ def dac_setup(self):

self.ad9154.dac_write(AD9154_SPI_PAGEINDX, 0x3) # A and B dual

self.ad9154.dac_write(AD9154_INTERP_MODE, 1) # 2x
self.ad9154.dac_write(AD9154_INTERP_MODE, 4) # 8x
self.ad9154.dac_write(AD9154_MIX_MODE, 0)
self.ad9154.dac_write(AD9154_DATA_FORMAT, AD9154_BINARY_FORMAT_SET(0)) # s16
self.ad9154.dac_write(AD9154_DATAPATH_CTRL,
15 changes: 7 additions & 8 deletions artiq/examples/phaser/repository/sawg.py
Original file line number Diff line number Diff line change
@@ -14,19 +14,18 @@ def build(self):
@kernel
def run(self):
self.core.break_realtime()
delay(100*us)

self.sawg0.set_amplitude(.1)
self.sawg1.set_amplitude(-.9)
self.sawg2.set_amplitude(.5)
self.sawg3.set_amplitude(.5)
self.sawg0.set_frequency(1*MHz)
self.sawg1.set_frequency(10*MHz)
self.sawg2.set_frequency(20*MHz)
self.sawg3.set_frequency(20*MHz)
self.sawg0.set_frequency(10*MHz)
self.sawg0.set_phase(0.)
self.sawg1.set_amplitude(-.9)
self.sawg1.set_frequency(20*MHz)
self.sawg1.set_phase(0.)
self.sawg2.set_amplitude(.5)
self.sawg2.set_frequency(30*MHz)
self.sawg2.set_phase(0.)
self.sawg3.set_amplitude(.5)
self.sawg3.set_frequency(30*MHz)
self.sawg3.set_phase(.5)

for i in range(10):
12 changes: 4 additions & 8 deletions artiq/examples/phaser/startup_kernel.py
Original file line number Diff line number Diff line change
@@ -42,14 +42,10 @@ def clock_setup(self):
self.ad9154.clock_write(AD9516_OUT5, 2*AD9516_OUT5_POWER_DOWN)
self.ad9154.clock_write(AD9516_OUT8, 1*AD9516_OUT8_POWER_DOWN)

# DAC deviceclk, dclk/1
self.ad9154.clock_write(AD9516_DIVIDER_0_1, AD9516_DIVIDER_0_BYPASS)
self.ad9154.clock_write(AD9516_DIVIDER_0_2,
0*AD9516_DIVIDER_0_DIRECT_TO_OUTPUT |
0*AD9516_DIVIDER_0_DCCOFF)
self.ad9154.clock_write(AD9516_OUT1,
0*AD9516_OUT1_POWER_DOWN |
2*AD9516_OUT1_LVPECLDIFFERENTIAL_VOLTAGE)
# DAC deviceclk, clk/1
self.ad9154.clock_write(AD9516_DIVIDER_0_2, AD9516_DIVIDER_0_DIRECT_TO_OUTPUT)
self.ad9154.clock_write(AD9516_OUT1, 0*AD9516_OUT1_POWER_DOWN |
2*AD9516_OUT1_LVPECLDIFFERENTIAL_VOLTAGE)

# FPGA deviceclk, dclk/4
self.ad9154.clock_write(AD9516_DIVIDER_4_3, AD9516_DIVIDER_4_BYPASS_2)