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stpl: fix byte ordering
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enjoy-digital committed Oct 12, 2016
1 parent 9644a3a commit 12b8598
Showing 1 changed file with 2 additions and 2 deletions.
4 changes: 2 additions & 2 deletions artiq/examples/phaser/repository/test_ad9154_stpl.py
Original file line number Diff line number Diff line change
@@ -27,8 +27,8 @@ def stpl(self, i, data):
AD9154_SHORT_TPL_DAC_SEL_SET(i) |
AD9154_SHORT_TPL_SP_SEL_SET(0))
# set expected value
self.ad9154.dac_write(AD9154_SHORT_TPL_TEST_2, data & 0xff)
self.ad9154.dac_write(AD9154_SHORT_TPL_TEST_1, (data & 0xff00) >> 8)
self.ad9154.dac_write(AD9154_SHORT_TPL_TEST_1, data & 0xff)
self.ad9154.dac_write(AD9154_SHORT_TPL_TEST_2, (data & 0xff00) >> 8)
# enable stpl
self.ad9154.dac_write(AD9154_SHORT_TPL_TEST_0,
AD9154_SHORT_TPL_TEST_EN_SET(1) |

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