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SaymaAMC manual
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switakowski committed Feb 4, 2018

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168 changes: 168 additions & 0 deletions ARTIQ_EE/PCB_Sayma_AMC/Manual/SaymaAMC.tex
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\documentclass[12pt,a4paper,final,titlepage]{article}
\addtolength{\textwidth}{3cm}
\addtolength{\hoffset}{-1.5cm}
\addtolength{\textheight}{3cm}
\addtolength{\voffset}{-1.5cm}
\usepackage[utf8]{inputenc}
\usepackage[english]{babel}
\usepackage[T1]{fontenc}
\usepackage{textcomp}
\usepackage{gensymb}
\usepackage{amsmath}
\usepackage[textwidth=40]{todonotes}
%\usepackage{todonotes}
%\usepackage[disable]{todonotes}
\usepackage{titlesec}
\usepackage{amsfonts}
\usepackage{amssymb}
\usepackage{gensymb}
\usepackage{longtable}
\usepackage{makeidx}
\usepackage{indentfirst}
\usepackage{graphicx}

\usepackage{epstopdf}
\usepackage{lmodern}
\usepackage{color}
\usepackage{xcolor}
\usepackage{url}
\usepackage{subfiles}
\usepackage{hhline}
\usepackage{nameref}
\usepackage{float}
\usepackage{wrapfig}
\usepackage{lastpage}
\makeatletter
\newcommand*{\currentname}{\@currentlabelname}
\makeatother
\usepackage{caption}
\usepackage[printwatermark]{xwatermark}
\usepackage{pdfpages}
\usepackage{multirow}
\usepackage{svg}
\setsvg{inkscape = inkscape -z -D}
\usepackage[toc,page]{appendix}
\usepackage{caption}
\usepackage{listings}

\usepackage[printonlyused,withpage]{acronym}
\graphicspath{{./},{./img/}}
\newcommand{\figref}{Fig.~\ref}
%\renewcommand{\bibname}{References}
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\newwatermark*[allpages,color=lred,angle=-45,scale=1,xpos=105,ypos=118]{DRAFT}
\newwatermark*[allpages,scale=0.4,xpos=-57,ypos=120]{\includegraphics{img/logo.png}}
\newwatermark*[allpages,scale=0.3,xpos=-35,ypos=122]{\includegraphics{img/artiq.png}}
%\usepackage[left=2cm,right=2cm,top=2cm,bottom=2cm]{geometry}
\usepackage{fancyhdr}
\pagestyle{fancy}
\lhead{}
\rhead{\nazwa}
\rfoot{Page \thepage \hspace{1pt} of \pageref{LastPage}}
\usepackage{hyperref}
\hypersetup{
colorlinks,
citecolor=black,
filecolor=black,
linkcolor=black,
urlcolor=black
}
\sloppy


%-----------------------------------------------------------------------
\newcommand{\nazwa}{SAYMA AMC}




\pdfinfo{ /Author (ISE) /Title (\nazwa) /Keywords (XXXX) }


\renewcommand{\footrulewidth}{1pt}

\cfoot{}

\begin{document}


\input{tex/title.tex}
%\maketitle
\input{tex/hist.tex}
\clearpage


\listoftodos
\clearpage
\tableofcontents



\clearpage


\input{tex/wiki_utca.tex}
\clearpage

\input{tex/wiki_sayma.tex}
\clearpage

\input{tex/intro.tex}
\clearpage


\input{tex/description.tex}
\clearpage

\input{tex/view.tex}
\clearpage

\input{tex/routing.tex}
\clearpage

\input{tex/clocking.tex}
\clearpage

\input{tex/panel.tex}
\clearpage

\input{tex/fmc.tex}
\clearpage

\input{tex/usb-uart.tex}
\clearpage

\input{tex/jtag.tex}
\clearpage

\input{tex/fpga.tex}
\clearpage

\input{tex/power.tex}
\clearpage

\input{tex/mmc.tex}
\clearpage

\input{tex/housekeeping.tex}
\clearpage


\input{tex/signals.tex}
\clearpage

\input{tex/testing.tex}
\clearpage


\begin{appendix}

\input{tex/appendix.tex}

\end{appendix}

\end{document}
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1,168 changes: 1,168 additions & 0 deletions ARTIQ_EE/PCB_Sayma_AMC/Manual/tex/appendix.tex

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10 changes: 10 additions & 0 deletions ARTIQ_EE/PCB_Sayma_AMC/Manual/tex/clocking.tex
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\section{Clocking}

This section describes how and where clock signals are routed.

\begin{figure}[htbp!]
\centering
\includegraphics[scale=0.2]{img/clk.eps}\\
\caption{Clocks} \label{clocking}
\end{figure}

92 changes: 92 additions & 0 deletions ARTIQ_EE/PCB_Sayma_AMC/Manual/tex/description.tex
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%\section{Project description}
%
%The Sayma AMC is a Advanced Mezzanine Card carrier board to carry FMC cards and connect RTM modules.
%
%

\section{Functional specifications}

\noindent

\textbf{Programmable resources:}

\begin{itemize}
\item Xilinx Kintex UltraScale – XCKU040-1FFVA-1156C FPGA
\begin{itemize}
\item speed grade: -1
\item 20 GTH transceivers (Max Preformance 16.3 Gb/s)
\end{itemize}
\item MMC: LPC17762984
\end{itemize}

\textbf{Memory:}

\begin{itemize}
\item 512Mb DDR3 SDRAM (32-bit interface), 800MHz (clock)
\item 1Gb DDR3 SDRAM (64-bit interface), 800MHz (clock)
\item SPI Flash for FPGA configuration. Accessible by MMC
\item SPI Flash for user data storage
\item EEPROM with MAC and unique ID

\end{itemize}

\textbf{Connectivity:}

\begin{itemize}
\item 1 high pin count (HPC) FMC slot for single width mezzanine card
\item Micro-USB UART connected to FPGA or MMC
\item Stand-alone 12V power connector
\item MGT (Multi-Gigabit Transceiver) connected to:
\begin{itemize}
% \item FMC x1
\item RTM x16
\item Fat\_Pipe1 x2
% \item AMC P2P x4
% \item Port 0 – possibility connected to SATA
\item SFP x2
\end{itemize}
% \item RTM connector with 8 GTP routed to it. Compatible with Sayma RTM module.
\item Port 0 – possibility connected to SATA
\item RTM connector compatible with Sayma RTM module

\end{itemize}

\textbf{Supply:}

\begin{itemize}
\item Monitoring of voltage and Power supply for RTM 12V and FMC 12V
\item FMC VADJ fixed to 1V8
\item Monitoring current of all FMC buses
\item Stand-alone power connectore
% \item Czy Exar monitoruje powera?

\end{itemize}


\textbf{Clocking:}

\begin{itemize}
\item Clock recovery Si5324
\item UFL CLK input
\item SMA CLK output


\end{itemize}


\textbf{Other:}

\begin{itemize}
\item Temperature, voltage and current monitoring for critical power buses
\item Temperature monitoring: FMC1, supply, FPGA core, DDR memory
\item JTAG multiplexer (SCANSTA) for FMC access, local JTAG port and remote debug/Chipscope via Ethernet

\end{itemize}








102 changes: 102 additions & 0 deletions ARTIQ_EE/PCB_Sayma_AMC/Manual/tex/fmc.tex
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\section{FMC}



\begin{itemize}
\item VADJ: 1V8 @ 1A
\item FPGA Banks: 47HP and 48HP
\end{itemize}


The connector is compliant with ANSI/VITA 57.1 FMC-LPC Standard.\\

%---------------------------------------------------------FMC1
\begin{footnotesize}
\begin{longtable}{|p{7cm}|p{1cm}|p{5cm}|}
\hline
\multicolumn{3}{|c|}{\multirow{2}{*}{\textbf{\large{FMC1}}}}\\
\multicolumn{3}{|c|}{} \\ \hline
FPGA signal & FPGA ball & Signal on the board \\ \hline
IO\_L12P\_T1U\_N10\_GC\_47 & AA24 & FMC1\_CLK0\_M2C\_P \\ \hline
IO\_L12N\_T1U\_N11\_GC\_47 & AA25 & FMC1\_CLK0\_M2C\_N \\ \hline
IO\_L11P\_T1U\_N8\_GC\_47 & Y23 & FMC1\_CLK1\_M2C\_P \\ \hline
IO\_L11N\_T1U\_N9\_GC\_47 & AA23 & FMC1\_CLK1\_M2C\_N \\ \hline
IO\_L12P\_T1U\_N10\_GC\_48 & AC31 & FMC1\_GBTCLK0\_M2C\_P \\ \hline
IO\_L12N\_T1U\_N11\_GC\_48 & AC32 & FMC1\_GBTCLK0\_M2C\_N \\ \hline
IO\_L1P\_T0L\_N0\_DBC\_48 & AE27 & FMC1\_DP0\_M2C\_P \\ \hline
IO\_L1N\_T0L\_N1\_DBC\_48 & AF27 & FMC1\_DP0\_M2C\_N \\ \hline
IO\_L2P\_T0L\_N2\_48 & AE28 & FMC1\_DP0\_C2M\_P \\ \hline
IO\_L2N\_T0L\_N3\_48 & AF28 & FMC1\_DP0\_C2M\_N \\ \hline
IO\_L13P\_T2L\_N0\_GC\_QBC\_48 & AA32 & FMC1\_LA00\_CC\_P \\ \hline
IO\_L13N\_T2L\_N1\_GC\_QBC\_48 & AB32 & FMC1\_LA00\_CC\_N \\ \hline
IO\_L14P\_T2L\_N2\_GC\_48 & AB30 & FMC1\_LA01\_CC\_P \\ \hline
IO\_L14N\_T2L\_N3\_GC\_48 & AB31 & FMC1\_LA01\_CC\_N \\ \hline
IO\_L8P\_T1L\_N2\_AD5P\_48 & AF33 & FMC1\_LA02\_P \\ \hline
IO\_L8N\_T1L\_N3\_AD5N\_48 & AG34 & FMC1\_LA02\_N \\ \hline
IO\_L21P\_T3L\_N4\_AD8P\_48 & V33 & FMC1\_LA03\_P \\ \hline
IO\_L21N\_T3L\_N5\_AD8N\_48 & W34 & FMC1\_LA03\_N \\ \hline
IO\_L7P\_T1L\_N0\_QBC\_AD13P\_48 & AG31 & FMC1\_LA04\_P \\ \hline
IO\_L7N\_T1L\_N1\_QBC\_AD13N\_48 & AG32 & FMC1\_LA04\_N \\ \hline
IO\_L10P\_T1U\_N6\_QBC\_AD4P\_48 & AE33 & FMC1\_LA05\_P \\ \hline
IO\_L10N\_T1U\_N7\_QBC\_AD4N\_48 & AF34 & FMC1\_LA05\_N \\ \hline
IO\_L15P\_T2L\_N4\_AD11P\_48 & AC34 & FMC1\_LA06\_P \\ \hline
IO\_L15N\_T2L\_N5\_AD11N\_48 & AD34 & FMC1\_LA06\_N \\ \hline
IO\_L18P\_T2U\_N10\_AD2P\_48 & AC33 & FMC1\_LA07\_P \\ \hline
IO\_L18N\_T2U\_N11\_AD2N\_48 & AD33 & FMC1\_LA07\_N \\ \hline
IO\_L11P\_T1U\_N8\_GC\_48 & AD30 & FMC1\_LA08\_P \\ \hline
IO\_L11N\_T1U\_N9\_GC\_48 & AD31 & FMC1\_LA08\_N \\ \hline
IO\_L9P\_T1L\_N4\_AD12P\_48 & AE32 & FMC1\_LA09\_P \\ \hline
IO\_L9N\_T1L\_N5\_AD12N\_48 & AF32 & FMC1\_LA09\_N \\ \hline
IO\_L17P\_T2U\_N8\_AD10P\_48 & AA34 & FMC1\_LA10\_P \\ \hline
IO\_L17N\_T2U\_N9\_AD10N\_48 & AB34 & FMC1\_LA10\_N \\ \hline
IO\_L16P\_T2U\_N6\_QBC\_AD3P\_48 & AA29 & FMC1\_LA11\_P \\ \hline
IO\_L16N\_T2U\_N7\_QBC\_AD3N\_48 & AB29 & FMC1\_LA11\_N \\ \hline
IO\_L24P\_T3U\_N10\_48 & V31 & FMC1\_LA12\_P \\ \hline
IO\_L24N\_T3U\_N11\_48 & W31 & FMC1\_LA12\_N \\ \hline
IO\_L19P\_T3L\_N0\_DBC\_AD9P\_48 & W33 & FMC1\_LA13\_P \\ \hline
IO\_L19N\_T3L\_N1\_DBC\_AD9N\_48 & Y33 & FMC1\_LA13\_N \\ \hline
IO\_L23P\_T3U\_N8\_48 & U34 & FMC1\_LA14\_P \\ \hline
IO\_L23N\_T3U\_N9\_48 & V34 & FMC1\_LA14\_N \\ \hline
IO\_L22P\_T3U\_N6\_DBC\_AD0P\_48 & Y31 & FMC1\_LA15\_P \\ \hline
IO\_L22N\_T3U\_N7\_DBC\_AD0N\_48 & Y32 & FMC1\_LA15\_N \\ \hline
IO\_L20P\_T3L\_N2\_AD1P\_48 & W30 & FMC1\_LA16\_P \\ \hline
IO\_L20N\_T3L\_N3\_AD1N\_48 & Y30 & FMC1\_LA16\_N \\ \hline
IO\_L13P\_T2L\_N0\_GC\_QBC\_47 & W23 & FMC1\_LA17\_CC\_P \\ \hline
IO\_L13N\_T2L\_N1\_GC\_QBC\_47 & W24 & FMC1\_LA17\_CC\_N \\ \hline
IO\_L14P\_T2L\_N2\_GC\_47 & W25 & FMC1\_LA18\_CC\_P \\ \hline
IO\_L14N\_T2L\_N3\_GC\_47 & Y25 & FMC1\_LA18\_CC\_N \\ \hline
IO\_L16P\_T2U\_N6\_QBC\_AD3P\_47 & V22 & FMC1\_LA19\_P \\ \hline
IO\_L16N\_T2U\_N7\_QBC\_AD3N\_47 & V23 & FMC1\_LA19\_N \\ \hline
IO\_L17P\_T2U\_N8\_AD10P\_47 & T22 & FMC1\_LA20\_P \\ \hline
IO\_L17N\_T2U\_N9\_AD10N\_47 & T23 & FMC1\_LA20\_N \\ \hline
IO\_L18P\_T2U\_N10\_AD2P\_47 & V21 & FMC1\_LA21\_P \\ \hline
IO\_L18N\_T2U\_N11\_AD2N\_47 & W21 & FMC1\_LA21\_N \\ \hline
IO\_L15P\_T2L\_N4\_AD11P\_47 & U21 & FMC1\_LA22\_P \\ \hline
IO\_L15N\_T2L\_N5\_AD11N\_47 & U22 & FMC1\_LA22\_N \\ \hline
IO\_L10P\_T1U\_N6\_QBC\_AD4P\_47 & AB21 & FMC1\_LA23\_P \\ \hline
IO\_L10N\_T1U\_N7\_QBC\_AD4N\_47 & AC21 & FMC1\_LA23\_N \\ \hline
IO\_L8P\_T1L\_N2\_AD5P\_47 & AC22 & FMC1\_LA24\_P \\ \hline
IO\_L8N\_T1L\_N3\_AD5N\_47 & AC23 & FMC1\_LA24\_N \\ \hline
IO\_L9P\_T1L\_N4\_AD12P\_47 & AA20 & FMC1\_LA25\_P \\ \hline
IO\_L9N\_T1L\_N5\_AD12N\_47 & AB20 & FMC1\_LA25\_N \\ \hline
IO\_L7P\_T1L\_N0\_QBC\_AD13P\_47 & AA22 & FMC1\_LA26\_P \\ \hline
IO\_L7N\_T1L\_N1\_QBC\_AD13N\_47 & AB22 & FMC1\_LA26\_N \\ \hline
IO\_L6P\_T0U\_N10\_AD6P\_47 & AB25 & FMC1\_LA27\_P \\ \hline
IO\_L6N\_T0U\_N11\_AD6N\_47 & AB26 & FMC1\_LA27\_N \\ \hline
IO\_L24P\_T3U\_N10\_47 & V26 & FMC1\_LA28\_P \\ \hline
IO\_L24N\_T3U\_N11\_47 & W26 & FMC1\_LA28\_N \\ \hline
IO\_L23P\_T3U\_N8\_47 & V29 & FMC1\_LA29\_P \\ \hline
IO\_L23N\_T3U\_N9\_47 & W29 & FMC1\_LA29\_N \\ \hline
IO\_L22P\_T3U\_N6\_DBC\_AD0P\_47 & U26 & FMC1\_LA30\_P \\ \hline
IO\_L22N\_T3U\_N7\_DBC\_AD0N\_47 & U27 & FMC1\_LA30\_N \\ \hline
IO\_L21P\_T3L\_N4\_AD8P\_47 & W28 & FMC1\_LA31\_P \\ \hline
IO\_L21N\_T3L\_N5\_AD8N\_47 & Y28 & FMC1\_LA31\_N \\ \hline
IO\_L20P\_T3L\_N2\_AD1P\_47 & U24 & FMC1\_LA32\_P \\ \hline
IO\_L20N\_T3L\_N3\_AD1N\_47 & U25 & FMC1\_LA32\_N \\ \hline
IO\_L19P\_T3L\_N0\_DBC\_AD9P\_47 & V27 & FMC1\_LA33\_P \\ \hline
IO\_L19N\_T3L\_N1\_DBC\_AD9N\_47 & V28 & FMC1\_LA33\_N \\ \hline
VREF\_48 & AA30 & FMC1\_VREF\_A\_M2C \\ \hline
VREF\_47 & V24 & FMC1\_VREF\_A\_M2C \\ \hline

\end{longtable}
\end{footnotesize}
12 changes: 12 additions & 0 deletions ARTIQ_EE/PCB_Sayma_AMC/Manual/tex/fpga.tex
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\section{FPGA bootstrapping}


\noindent
\textbf{Xilinx User Guide:} \href{https://www.xilinx.com/support/documentation/user_guides/ug570-ultrascale-configuration.pdf}{https://www.xilinx.com/support/documentation/user\_guides/ug570-ultrascale-configuration.pdf}\\

To load FPGA .bit into flash Vivado in version minimum 16.4 is needed.\\
\textbf{Vivado WebPack:}\href{https://www.xilinx.com/support/download.html}{https://www.xilinx.com/support/download.html}

Alternatively Vivado Lab tools (previously Lab Tools) can be used.\\
\textbf{Vivado Lab Edition:}\href{https://www.xilinx.com/support/download.html}{https://www.xilinx.com/support/download.html}

18 changes: 18 additions & 0 deletions ARTIQ_EE/PCB_Sayma_AMC/Manual/tex/hist.tex
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\begin{table}[h!]
\vspace{5cm}
\centering
\begin{center}
\begin{tabular}{|l|l|}
\hline
\textbf{\rule[-2ex]{0pt}{5.5ex} Document version:} & Preliminary \\ \hline
\textbf{\rule[-2ex]{0pt}{5.5ex} Issue Date:} & \today \\ \hline
\textbf{\rule[-2ex]{0pt}{5.5ex} Written by:} & Filip Świtakowski \\ \hline
\textbf{\rule[-2ex]{0pt}{5.5ex} Approved by:} & Greg Kasprowicz \\ \hline
\textbf{\rule[-2ex]{0pt}{5.5ex} Document title:} & \nazwa - specification \\ \hline

\end{tabular}
\end{center}
\end{table}
39 changes: 39 additions & 0 deletions ARTIQ_EE/PCB_Sayma_AMC/Manual/tex/housekeeping.tex
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\section{Housekeeping Signals}
\subsection{sensors}
Temperature:\\
%\begin{itemize}
% \item IC8 (0x4B) -NOR Flash
% \item IC34 (0x49) -FPGA
% \item IC35 (0x4A)-under SFPs
% \item IC36 (0x4F)-power section
% \item IC37 (0x24) -middle od the board
%\end{itemize}
\begin{longtable}{|c|c|c|c|c|}\hline
No & Addr. & placement & Type & Accuracy \\ \hline
IC8 & 0x4B & NOR Flash & LM75 & +/- 2 \\ \hline
IC34 & 0x49 & FPGA & LM75 & +/- 2 \\ \hline
IC35 & 0x4A & Under SFPs & LM75 & +/- 2 \\ \hline
IC36 & 0x4F & power section & LM75 & +/- 2 \\ \hline
IC37 & 0x24 & middle of the board & MAX664A & +/- 1 \\ \hline
\end{longtable}

All temperature sensors are tied tohether to one I2C bus - I2C\_SENS. \\


Current:
%\begin{itemize}
% \item IC27 (0x40)-RTM\_P12V0
% \item IC28 (0x41)-FMC\_P12V0
%\end{itemize}
\begin{longtable}{|c|c|c|c|c|}\hline
No & Addr. & placement & Type & Accuracy \\ \hline
IC27 & 0x40 &RTM\_P12V0& INA219 & +/- 0.2\% \\ \hline
IC28 & 0x41 &FMC\_P12V0& INA219 & +/- 0.2\% \\ \hline
\end{longtable}


All current sensors are tied tohether to one I2C bus - PM\_I2C. \\

\subsection{Safety interlocks}

\todo[inline]{TBD OVERTEMPn}
49 changes: 49 additions & 0 deletions ARTIQ_EE/PCB_Sayma_AMC/Manual/tex/intro.tex
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%\section{Introduction to Micro TCA}




%The MTCA platform is available on the market for over
%ten years. It evolved from telecommunication ATCA standard. The MTCA sandard utilizes ATCA-defined AMC boards
%used directly in dedicated chassis. It also defines MTCA
%Carrier Hub (MCH) which controlls multiple slave boards, known as Advanced Mezzanine Cards (AMCs) via a high-speed digital backplane. AMC card can be equipped with FPGA Mzzanine Cards (FMCs) which are I/O modules pluggable to High-pin Count (HPC) or Low-pin Count (LPC) connector.
%
%%which consists of Ethernet hub and crate
%%management system.
%The MTCA crates are available in several
%form-factors for industrial, aviation and military use.
%User can easily extend and adopt the standard to particular application by selection of
%proper chassis, cooling method, computing and connectivity
%technology while keeping same mechanical, electrical standard and software architecture.\\


%MicroTCA (uTCA) is Sinara's preferred form-factor for hardware with high-speed data converters requiring deterministic phase control, such as the Sayma 2.4GSPS smart arbitrary waveform generator (SAWG).
%
%uTCA is a modular, open standard originally developed by the telecommunications industry. It allows a single rack master -- the Micro TCA Carrier Hub (MCH) -- to control multiple slave boards, known as Advanced Mezzanine Cards (AMCs) via a high-speed digital backplane. uTCA chassis and backplanes are available commercially of the shelf (COTS).
%%
%We make use of the most recent extension to the uTCA standard, uTCA.4. Originating in the high-energy and particle physics (HEPP) community, uTCA.4 introduces rear-transition modules (RTMs) along with a second backplane for low-noise RF signals (RFBP). Each RTM connects to an AMC (one RTM per AMC). Typically, the AMCs hold FPGAs and other high-speed digital hardware, communicating with the MCH via gigabit serial links over the AMC backplane. The RTMs hold data converters and other low-noise analog components, controlled by the corresponding AMC. The RFBP provides low-noise clocks and local oscillators (LOs). The RTMs and RFBP are screened from the AMCs to minimise interference from the high-speed digital logic

\section{Glossary}

\begin{description}
\item[AMC Module or Modul] An AMC Module is a mezzanine or modular add-on card that extends the
functionality of a Carrier Board. The term is also used to generically refer to the
different varieties of Multi-Width and Multi-Height Modules.
\item[Fat Pipes] Ports 4 though 11 of the AMC Connector constitute the Fat Pipes Region. This
Region of Ports is intended for the assignment of multiple Lane interfaces, also
called “fat pipes”. Fat Pipe 1 [Ports 4-7], Fat Pipe [Ports 8-11].
\item[FMC] FPGA Mezzanine Card
\item[Hot Swap] To remove a component (e.g., an AMC Module) from a system (e.g., an AMC Carrier
AdvancedTCA Board) and plug in a new one while the power is still on and the
system is still operating.
\item[Management Power or MP] The 3.3V power for a Module's Management function, individually provided to each Slot by the Carrier
\item[IPMB] ntelligent Platform Management Bus. The lowest level hardware management bus
as described in the Intelligent Platform Management Bus Communications Protocol
Specification.
\item[MGT] Multi-Gigabit Transceiver
\item[MMC] Module Management Controller. The MMC is the required intelligent controller that
manages the Module and is interfaced to the Carrier via IPMB-Local
\item[RTM] Rear Transition Module
\end{description}


31 changes: 31 additions & 0 deletions ARTIQ_EE/PCB_Sayma_AMC/Manual/tex/jtag.tex
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\section{JTAG}

JTAG can be connected either from USB (FT4232H) or from IDC header. IDC header is permanenty connected to Scansta. \\
The USB-UART bridge can be enabled by setting high on ADBUS7.\\



\begin{figure}[htbp!]
\centering
\includegraphics[scale=0.5]{img/jtag.png}\\
\caption{USB-->JTAG}
\end{figure}
General block scheme of Scansta connections is shown below.\\

\begin{figure}[htbp!]
\centering
\includegraphics[scale=0.4]{img/scansta.eps}\\
\caption{SCANSTA bloch scheme}
\end{figure}

\textit{\textbf{Note:} The FMC2 and PS is not used.}\\

Scansta112 is 7-Port Multidrop JTAG Multiplexer. It is used to partition scan chains into managable sizes, or to isolate specific devices onto a separate chain. By default Scansta input signal is from IDC header. AMC JTAG is connected to Master Port on SCANSTA, so it can be used as Master or Slave module. The rest modules (MMC, FPGA, FMC, RTM) are tied to slave SCANSTA outputs. \\
Simplified instruction if using SCANSTA can be found under: \href{http://www.ti.com/lit/an/snla068c/snla068c.pdf}{http://www.ti.com/lit/an/snla068c/snla068c.pdf}
In Sayma AMC, SCANSTA112 is used in Transparent Sticher Mode. In this mode, the IC can be configured via hardware to skip the addressing protocol needed, sothere is no need to run a SVF configuration file on IMPACT when programming the FPGA bitstream.

\begin{figure}[htbp!]
\centering
\includegraphics[scale=0.4]{img/jtagchain.eps}\\
\caption{SCANSTA JTAG chain}
\end{figure}
70 changes: 70 additions & 0 deletions ARTIQ_EE/PCB_Sayma_AMC/Manual/tex/mmc.tex
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\section{MMC}

\subsection{MMC steps during booting}

\begin{itemize}

\item configures CPU, UART
\item sets port directions
\item enables VCCINT PSU
\item enables P5V0 PSU (helper PSU)
\item enables Exar PSU. It boots from its own EEPROM
\item waits 200ms
\item configures SCANSTA chip in stitcher mode. If RTM is inserted, it enables its JTAG port
\item configures I2C switch base address
\item initializes default RTM power state to off
\item initializes Ethernet PHY chip in RGMII mode using pin strap.
\item waits 200ms
\item initializes I2C controller and chain (switch)
\item configures Si5324
\item checks if RTM is inserted, if yes, then enables its power, waits 200ms and initializes RTM power supply via I2C. It also configures Si5324 on RTM
\item runs task.\\

The task performs following functions:

\item blinks front panel LEDs alternately
\item checks if FPGA is configured. If not, it keeps Ethernet PHY in reset state. Once FPGA gets configured, it initializes the PHY.
\item checks if RTM is unplugged. If not, it switches the power off to make sure it is off during hotplug.
\end{itemize}

\subsection{Bootstraping}

The MMC can be upgraded by USB cable and NXP programmer(can be used other programmer but make sure that header shorts pins 3, 5, 9) using \href{http://www.flashmagictool.com/}{Flashmagic} or any other software which can talk with NXP bootloader. The source code is written in C and can be found on github.\\
\textbf{Source code:} \href{https://github.com/m-labs/sinara/tree/master/SAYMA\_firmware}{https://github.com/m-labs/sinara/tree/master/SAYMA\_firmware}.\\
\textbf{pre-compiled binary:} \href{https://github.com/m-labs/mmc-firmware/releases}{https://github.com/m-labs/mmc-firmware/releases}\\

To compile binaries \href{https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/lpc-cortex-m-mcus/lpc1100-cortex-m0-plus-m0/lpcxpresso-ide-v8.2.2:LPCXPRESSO?tab=Design_Tools_Tab}{LPCXpresso} is needed.

\subsection{Functionality}

\todo[inline]{needed?}

\subsection{Exar debugging}

In case of chip failure, i.g.overvoltage, overcurrent, etc., there is possibility to check chip status via UART. In this case in UART console, Exar register readout can be done by typing 'P' character.\\

\begin{figure}[htbp!]
\centering
\includegraphics[scale=0.6]{img/exarreg.png}\\
\caption{Exar register }
\end{figure}
\clearpage
\subsection{PHY debugging}

In case of chip failure, there is possibility to check chip status via UART. In this case in UART console, Ethernet PHY content can be read by typing 'E' character

\begin{figure}[htbp!]
\centering
\includegraphics[scale=0.6]{img/phyreg.png}\\
\caption{Ethernet PHY register }
\end{figure}

\subsection{RGMII Ethernet }

\todo[inline]{TBD. Not sure what should it contain.}

\subsection{OpenMMC}

\textbf{OpenMMC Project:}\href{https://github.com/lnls-dig/openMMC}{https://github.com/lnls-dig/openMMC}

\todo[inline]{TBD}
173 changes: 173 additions & 0 deletions ARTIQ_EE/PCB_Sayma_AMC/Manual/tex/panel.tex
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\section{Front panel and headers}

\begin{figure}[htbp!]
\centering
\includegraphics[width=14cm]{img/frontcallout.png}\\
\caption{Front view}
\end{figure}

\begin{figure}[htbp!]
\centering
\includegraphics[width=14cm]{img/topcallout1.png}\\
\caption{Front view}
\end{figure}
\clearpage
\begin{figure}[htbp!]
\centering
\includegraphics[width=14cm]{img/botcallout1.png}\\
\caption{Front view}
\end{figure}

\begin{longtable}{|c|c|c|} \hline
\multicolumn{3}{|c|}{Call out table } \\ \hline
Call out & Designator & Description \\ \hline
1 & J15 & IO1 \\ \hline
2 & J26 & IO2 \\ \hline
3 & J27 & CLK OUT \\ \hline
4 & -- & FMC slot \\ \hline
% 5 & LD13 & Error\\ \hline
% 6 & LD18 & Hot swap \\ \hline
7 & PB3 & reset? \\ \hline
8 & cage2 & SFP Cage \\ \hline
9 & cage1 & SFP Cage \\ \hline
10 & J1 & Micro USB -->Serial \\ \hline
% 11& LD14 & operation successful \\ \hline
% 12 & LD16 & SFP LED2 \\ \hline
% 13 & LD3 & SFP LED1 \\ \hline
% 14 & LD6 & LINK UP \\ \hline
% 15 & LD4 & MII MODE \\ \hline
% 16 & LD15 & SFP LED2 \\ \hline
% 17 & LD2 & SFP LED1 \\ \hline
% 18 & LD5 & FPGA ETH \\ \hline
19 & J28 & FMC Header \\ \hline
20 & J3 & SW JTAG \\ \hline
21 & J14 & MMC JTAG \\ \hline
22 & SW1 & FPGA MODE \\ \hline
23 & J13 & Digital IOs \\ \hline
24 & J12 & SLAVE SATA \\ \hline
25 & J11 & MASTER SATA \\ \hline
26 & J4 & Power In \\ \hline
27 & J10 & Port 0 \\ \hline
28 & W1 & EXAR I2C header \\ \hline
29 & -- & P12V0 \\ \hline
30 & -- & Test points \\ \hline
\end{longtable}

\begin{longtable}{|c|c|c|c|c|c|c|} \hline
\multicolumn{7}{|c|}{LED table }\\ \hline
Call out & Designator & Description& Colour &nominal state& IC &Failure\\ \hline
5 & LD13 & Error &Red & off &MMC & on \\ \hline
6 & LD4 & Hot Swap & Blue & on& MMC & off\\ \hline
6 & LD21 & FPGA config done & Green & on& FPGA &off \\ \hline
11 & LD14 & Operation succesful& Green & on& MMC &off\\ \hline
12 & LD3 & SFP2 LED2 & Red &on& FPGA & off\\ \hline
13 & LD6 & SFP2 LED1 & Green &on & FPGA&off \\ \hline
14 & LD20 & LINK UP & Green &on & MAX24287&off \\ \hline
15 & LD18 & MII MODE & Green & on& MMC&off \\ \hline
16 & LD2 & SFP1 LED2 & Red & on& FPGA &off\\ \hline
17& LD5 & SFP1 LED1 & Green &on & FPGA& off\\ \hline
18 & LD19 & FPGA ETH & Green &on & MMC &off\\ \hline
30 & LD22 & 3V3 & Green & on & Power & off \\ \hline
30 & LD7 & 0V95 & Green & on & Power & off \\ \hline
30 & LD11 & 0V9 & Green & on & Power & off \\ \hline
30 & LD8 & 1V5 & Green & on & Power & off \\ \hline
30 & LD9 & 1V8 & Green & on & Power & off \\ \hline
30 & LD10 & 12V & Green & on & Power & off \\ \hline
\end{longtable}

\subsection{Headers pinout}

\begin{figure}[htbp!]
\centering
\includegraphics[width=9cm]{img/jtag1.png}\\
\caption{JTAG - Call out 20}
\end{figure}

\begin{figure}[htbp!]
\centering
\includegraphics[width=9cm]{img/jtaglpc.png}\\
\caption{JTAG - Call out 21}
\end{figure}

\begin{figure}[htbp!]
\centering
\includegraphics[width=9cm]{img/gpio.png}\\
\caption{DIO - Call out 23}
\end{figure}

\clearpage


\begin{longtable}{|c|c|c|} \hline
\multicolumn{3}{|c|}{Tespoints table - Call out 30}\\ \hline
TPx & Sig Name & LPC pin \\ \hline
TP1 & MII1\_col & C13 \\ \hline
TP2 & SDCLK & J10 \\ \hline
TP3 & SDCMD & K14 \\ \hline
TP4 & SDPWR & K11 \\ \hline
TP5 & SDDAT0 & L14 \\ \hline
TP6 & SDDAT1 & M12 \\ \hline
TP7 & SDDAT2 & N14 \\ \hline
TP8 & SDDAT3 & M11 \\ \hline

\end{longtable}


\subsection{Location ICs}

\begin{figure}[htbp!]
\centering
\includegraphics[width=14cm]{img/TU1.png}\\
\caption{Top}
\end{figure}
\begin{figure}[htbp!]
\centering
\includegraphics[width=14cm]{img/BU1.png}\\
\caption{Bot}
\end{figure}
\clearpage

\begin{longtable}{|c|c|c|} \hline
\multicolumn{3}{|c|}{ICs Location}\\ \hline
Ux & IC & Description \\ \hline
U1 & Kintex& FPGA \\ \hline
U2 & LTC 6957&Low Phase Noise Buffer \\ \hline
U4 & TPS53353 & P0V9\\ \hline
U5 & XR77129 & EXAR\\ \hline
U6 & TPS 74401 & P1V2\\ \hline
U7 & TPS 74401 & P0V95 \\ \hline
U3 & SI5324C& Clock recovery \\ \hline
U8 & TCA9548 &I2C switch - MMC\\ \hline
U9 & TCA9548 &I2C switch - FPGA\\ \hline
U10 & 74HC4066PW & Analog switch - Flash update\\ \hline
U11 & N25Q256A13ESF40 & NOR Flash\\ \hline
U12 & N25Q256A13ESF40 & NOR Flash\\ \hline
U13 & SN74CB3Q32245ZKE & Digital Bus switch - RGMI/MII\\ \hline
U14 & LPC1776FET180 & MMC\\ \hline
U15 & MAX24287ETK+ &ETH switch\\ \hline
U16 & AN74CBT3257PW & USB console switch\\ \hline
U17 & N25Q256A13ESF40 & NOR Flash - MMC\\ \hline
U18 & M93C46 & EEPROM\\ \hline
U19 & F4232H-56Q & USB-UART Bridge \\ \hline
U20 & 74HC4066PW & USB-UART Switch\\ \hline
U21 & SCANSTA112SM & SCANSTA JTAG Switch\\ \hline
U22 & FDMS7608S &EXAR Transistors \\ \hline
U23 & SN65MLVD040RGZT &LVDS transceiver\\ \hline
U24 & SN65MLVD040RGZT &LVDS transceiver \\ \hline
U25 & TPS62175 & P5V0 \\ \hline
U26 & TPS62175 & P3V3 \\ \hline
\end{longtable}


\subsection{SW1}

\begin{longtable}{|c|c|c|c|} \hline
\multicolumn{4}{|c|}{SW1 table}\\ \hline
M0 & M1 & M2 & Description \\ \hline
0 & 0 & 0 & Master Serial Mode \\ \hline
0 & 0 & 1 & Master Parallel Up \\ \hline
0 & 1 & 1 & Master Parallel Down \\ \hline
1 & 0 & 1 & Peripheral mode \\ \hline
1 & 1 & 1 & Slave Serial mode \\ \hline

\end{longtable}
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\section{Power}
\subsection{Power supply}

\todo[inline]{TBD voltage noise}
The 12V power can be connected either from AMC connector or from Stand alone power supply connected to Molex Connector(39-28-1043).

\begin{figure}[htbp!]
\centering
\includegraphics[scale=0.2]{img/molex.jpg}\\
\caption{Power connector}
\end{figure}
\begin{center}
\begin{tabular}{|c|c|} \hline
{\LARGE GND} & {\LARGE GND} \\ \hline
{\LARGE +12} & {\LARGE +12} \\ \hline
\end{tabular}
\end{center}

Maximum board(AMC+RTM module) power consumption estimate to 3A @ 12V.\\

\textit{\textbf{Note:} Please note that power consumption mostly depends from FPGA configuration. \\}

\begin{itemize}


\item Input voltage range: 10.8-13.2 [V]\\
\item The board needs active cooling. Approx. 20CFM in 20 C air.\\

\end{itemize}
\subsection{Power configuration}

\subsubsection{Power map}


\begin{figure}[htbp!]
\centering
\includegraphics[scale=0.3]{img/pwr.eps}\\
\caption{Power map}
\end{figure}
\clearpage

\begin{longtable}{|c|c|c|} \hline
\multicolumn{3}{|c|}{voltages and currents} \\ \hline
P0V9 & 0.9V & 10A \\ \hline
P0V95 & 0.95V & 31mA\\ \hline
P1V0 & 1.0V & 3A\\ \hline
P1V2 & 1.2V & 0.6A\\ \hline
P1V5 & 1.5V & 7.5A\\ \hline
P1V8 & 1.8V & 1.6A\\ \hline
P3V3 & 3.3 V & 2A\\ \hline
P3V3MP & 3.3V & 0.18A \\ \hline
P5V0 & 5.0V & 0.5A\\ \hline
\end{longtable}

\begin{longtable}{|c|c|c|} \hline
\multicolumn{3}{|c|}{Maximum RTM voltages and currents} \\ \hline
P12V0 & 12V & 3A \\ \hline
P3V3MP\_RTM & 3.3V & 30mA \\ \hline
\end{longtable}

\subsubsection{Exar parameters}

Exar chip has 4 configurable outputs with configirable current limits. Channels 1, 3, 4 are power un on chip enable with 10ms delay. Channel 2 is power on 'EN\_PSU\_CH' signal. \\
%3V3 LDO is power on independently. \\

\begin{figure}[htbp!]
\centering
\includegraphics[scale=0.6]{img/exar1.png}\\
\caption{Exar configuration}
\end{figure}

\begin{figure}[htbp!]
\centering
\includegraphics[scale=0.6]{img/exar2.png}\\
\caption{Exar power on delays}
\end{figure}

\clearpage


\subsubsection{Exar configuration}
Exar chips are configured via I2C bus (MUX Port 5) or directly by connecting to W1 (call-out 28) header. For proper configuration \textbf{Exar Power Architect} in version \textbf{5.2-r1} is needed.
% Configuration files can be found at github in folder \href{https://github.com/m-labs/sinara/tree/master/EXAR\_config}{m-labs/sinara/Exar\_config}\\

\noindent
\textbf{Exar Power Archtect 5.2-r1:}
\href{https://www.exar.com/content/document.ashx?id=21632}{https://www.exar.com/content/document.ashx?id=21632}\\
\textbf{Configuration files:}
\href{https://github.com/m-labs/sinara/tree/master/EXAR\_config}{https://github.com/m-labs/sinara/tree/master/EXAR\_config}\\
\textbf{Datasheet:}\href{https://www.exar.com/ds/xr77129_1a_120514.pdf}{https://www.exar.com/ds/xr77129\_1a\_120514.pdf}\\
\textbf{Quick Start Guide:} \href{https://www.exar.com/files/powerxr/PA5-QSG_110_010614.pdf}{https://www.exar.com/files/powerxr/PA5-QSG\_110\_010614.pdf}\\


Actual voltages and current consumption, temperature can be found in Chip Dashboard. There is also oportunity to adjust settings.

\begin{figure}[htbp!]
\centering
\includegraphics[scale=0.6]{img/exarprog.png}\\
\caption{Chip Dashboard}
\end{figure}


24 changes: 24 additions & 0 deletions ARTIQ_EE/PCB_Sayma_AMC/Manual/tex/routing.tex
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\section{Routing}


This section contain general bloch scheme of SAYMA AMC board and I2C map with addresses. General Block Scheme -figure \ref{BlockScheme}
shows more importand connections between components. I2C connections with addresses can be found in figure \ref{I2C}. Detailed clocking scheme can be found in next paragraph in figure \ref{clocking}.
\begin{figure}[htbp!]
\centering
\includegraphics[scale=0.2]{img/sch.eps}\\
\caption{General Block Scheme}\label{BlockScheme}
\end{figure}


\begin{figure}[htbp!]
\centering
\includegraphics[scale=0.2]{img/sch_mgt.eps}\\
\caption{MGT} \label{MGT}
\end{figure}

\begin{figure}[htbp!]
\centering
\includegraphics[scale=0.2]{img/i2c.eps}\\
\caption{I2C} \label{I2C}
\end{figure}

285 changes: 285 additions & 0 deletions ARTIQ_EE/PCB_Sayma_AMC/Manual/tex/signals.tex
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\section{Signal tables}
In this section the more important signals tables are presented. The total signal table is in Appendix section.\\
%---------------------------------------------------------SFP1
\begin{footnotesize}
\begin{longtable}{|p{7cm}|p{1cm}|p{5cm}|}
\hline
\multicolumn{3}{|c|}{\multirow{2}{*}{\textbf{\large{SFP1}}}}\\
\multicolumn{3}{|c|}{} \\ \hline
FPGA signal & FPGA ball & Signal on the board \\ \hline
MGTHTXN0\_224 & AN3 & SFP1TX\_N \\ \hline
MGTHTXP0\_224 & AN4 & SFP1TX\_P \\ \hline
MGTHRXN0\_224 & AP1 & SFP1RX\_N \\ \hline
MGTHRXP0\_224 & AP2 & SFP1RX\_P \\ \hline
IO\_L14N\_T2L\_N3\_GC\_64 & AG9 & SFP1\_LED1 \\ \hline
IO\_T2U\_N12\_64 & AJ10 & SFP1\_LED2 \\ \hline
IO\_L3P\_T0L\_N4\_AD15P\_64 & AM11 & SFP1\_LOS \\ \hline
IO\_L2N\_T0L\_N3\_64 & AP13 & SFP1\_MOD\_DEF2 \\ \hline
IO\_L2P\_T0L\_N2\_64 & AN13 & SFP1\_MOD\_DEF1 \\ \hline
IO\_L3N\_T0L\_N5\_AD15N\_64 & AN11 & SFP1\_MOD\_DEF0 \\ \hline
IO\_T0U\_N12\_64 & AK11 & SFP1\_RATE\_SELECT \\ \hline
IO\_L1P\_T0L\_N0\_DBC\_64 & AP11 & SFP1\_TX\_DISABLE \\ \hline
IO\_L1N\_T0L\_N1\_DBC\_64 & AP10 & SFP1\_TX\_FAULT \\ \hline



\end{longtable}
\end{footnotesize}

%---------------------------------------------------------SFP2
\begin{footnotesize}
\begin{longtable}{|p{7cm}|p{1cm}|p{5cm}|}
\hline
\multicolumn{3}{|c|}{\multirow{2}{*}{\textbf{\large{SFP2}}}}\\
\multicolumn{3}{|c|}{} \\ \hline
FPGA signal & FPGA ball & Signal on the board \\ \hline
MGTHTXN1\_224 & AM5 & SFP2TX\_N \\ \hline
MGTHTXP1\_224 & AM6 & SFP2TX\_P \\ \hline
MGTHRXN1\_224 & AM1 & SFP2RX\_N \\ \hline
MGTHRXP1\_224 & AM2 & SFP2RX\_P \\ \hline
IO\_L8N\_T1L\_N3\_AD5N\_64 & AJ13 & SFP2\_LED1 \\ \hline
IO\_L7P\_T1L\_N0\_QBC\_AD13P\_64 & AE13 & SFP2\_LED2 \\ \hline
IO\_L7N\_T1L\_N1\_QBC\_AD13N\_64 & AF13 & SFP2\_LOS \\ \hline
IO\_L5P\_T0U\_N8\_AD14P\_64 & AK12 & SFP2\_MOD\_DEF2 \\ \hline
IO\_L6N\_T0U\_N11\_AD6N\_64 & AL13 & SFP2\_MOD\_DEF1 \\ \hline
IO\_L6P\_T0U\_N10\_AD6P\_64 & AK13 & SFP2\_MOD\_DEF0 \\ \hline
IO\_L5N\_T0U\_N9\_AD14N\_64 & AL12 & SFP2\_RATE\_SELECT \\ \hline
IO\_L4P\_T0U\_N6\_DBC\_AD7P\_64 & AM12 & SFP2\_TX\_DISABLE \\ \hline
IO\_L4N\_T0U\_N7\_DBC\_AD7N\_64 & AN12 & SFP2\_TX\_FAULT \\ \hline



\end{longtable}
\end{footnotesize}

%%---------------------------------------------------------FMC1
%\begin{footnotesize}
% \begin{longtable}{|p{7cm}|p{1cm}|p{5cm}|}
% \hline
% \multicolumn{3}{|c|}{\multirow{2}{*}{\textbf{\large{FMC1}}}}\\
% \multicolumn{3}{|c|}{} \\ \hline
%IO\_L12P\_T1U\_N10\_GC\_47 & AA24 & FMC1\_CLK0\_M2C\_P \\ \hline
%IO\_L12N\_T1U\_N11\_GC\_47 & AA25 & FMC1\_CLK0\_M2C\_N \\ \hline
%IO\_L11P\_T1U\_N8\_GC\_47 & Y23 & FMC1\_CLK1\_M2C\_P \\ \hline
%IO\_L11N\_T1U\_N9\_GC\_47 & AA23 & FMC1\_CLK1\_M2C\_N \\ \hline
%IO\_L12P\_T1U\_N10\_GC\_48 & AC31 & FMC1\_GBTCLK0\_M2C\_P \\ \hline
%IO\_L12N\_T1U\_N11\_GC\_48 & AC32 & FMC1\_GBTCLK0\_M2C\_N \\ \hline
%IO\_L1P\_T0L\_N0\_DBC\_48 & AE27 & FMC1\_DP0\_M2C\_P \\ \hline
%IO\_L1N\_T0L\_N1\_DBC\_48 & AF27 & FMC1\_DP0\_M2C\_N \\ \hline
%IO\_L2P\_T0L\_N2\_48 & AE28 & FMC1\_DP0\_C2M\_P \\ \hline
%IO\_L2N\_T0L\_N3\_48 & AF28 & FMC1\_DP0\_C2M\_N \\ \hline
%IO\_L13P\_T2L\_N0\_GC\_QBC\_48 & AA32 & FMC1\_LA00\_CC\_P \\ \hline
%IO\_L13N\_T2L\_N1\_GC\_QBC\_48 & AB32 & FMC1\_LA00\_CC\_N \\ \hline
%IO\_L14P\_T2L\_N2\_GC\_48 & AB30 & FMC1\_LA01\_CC\_P \\ \hline
%IO\_L14N\_T2L\_N3\_GC\_48 & AB31 & FMC1\_LA01\_CC\_N \\ \hline
%IO\_L8P\_T1L\_N2\_AD5P\_48 & AF33 & FMC1\_LA02\_P \\ \hline
%IO\_L8N\_T1L\_N3\_AD5N\_48 & AG34 & FMC1\_LA02\_N \\ \hline
%IO\_L21P\_T3L\_N4\_AD8P\_48 & V33 & FMC1\_LA03\_P \\ \hline
%IO\_L21N\_T3L\_N5\_AD8N\_48 & W34 & FMC1\_LA03\_N \\ \hline
%IO\_L7P\_T1L\_N0\_QBC\_AD13P\_48 & AG31 & FMC1\_LA04\_P \\ \hline
%IO\_L7N\_T1L\_N1\_QBC\_AD13N\_48 & AG32 & FMC1\_LA04\_N \\ \hline
%IO\_L10P\_T1U\_N6\_QBC\_AD4P\_48 & AE33 & FMC1\_LA05\_P \\ \hline
%IO\_L10N\_T1U\_N7\_QBC\_AD4N\_48 & AF34 & FMC1\_LA05\_N \\ \hline
%IO\_L15P\_T2L\_N4\_AD11P\_48 & AC34 & FMC1\_LA06\_P \\ \hline
%IO\_L15N\_T2L\_N5\_AD11N\_48 & AD34 & FMC1\_LA06\_N \\ \hline
%IO\_L18P\_T2U\_N10\_AD2P\_48 & AC33 & FMC1\_LA07\_P \\ \hline
%IO\_L18N\_T2U\_N11\_AD2N\_48 & AD33 & FMC1\_LA07\_N \\ \hline
%IO\_L11P\_T1U\_N8\_GC\_48 & AD30 & FMC1\_LA08\_P \\ \hline
%IO\_L11N\_T1U\_N9\_GC\_48 & AD31 & FMC1\_LA08\_N \\ \hline
%IO\_L9P\_T1L\_N4\_AD12P\_48 & AE32 & FMC1\_LA09\_P \\ \hline
%IO\_L9N\_T1L\_N5\_AD12N\_48 & AF32 & FMC1\_LA09\_N \\ \hline
%IO\_L17P\_T2U\_N8\_AD10P\_48 & AA34 & FMC1\_LA10\_P \\ \hline
%IO\_L17N\_T2U\_N9\_AD10N\_48 & AB34 & FMC1\_LA10\_N \\ \hline
%IO\_L16P\_T2U\_N6\_QBC\_AD3P\_48 & AA29 & FMC1\_LA11\_P \\ \hline
%IO\_L16N\_T2U\_N7\_QBC\_AD3N\_48 & AB29 & FMC1\_LA11\_N \\ \hline
%IO\_L24P\_T3U\_N10\_48 & V31 & FMC1\_LA12\_P \\ \hline
%IO\_L24N\_T3U\_N11\_48 & W31 & FMC1\_LA12\_N \\ \hline
%IO\_L19P\_T3L\_N0\_DBC\_AD9P\_48 & W33 & FMC1\_LA13\_P \\ \hline
%IO\_L19N\_T3L\_N1\_DBC\_AD9N\_48 & Y33 & FMC1\_LA13\_N \\ \hline
%IO\_L23P\_T3U\_N8\_48 & U34 & FMC1\_LA14\_P \\ \hline
%IO\_L23N\_T3U\_N9\_48 & V34 & FMC1\_LA14\_N \\ \hline
%IO\_L22P\_T3U\_N6\_DBC\_AD0P\_48 & Y31 & FMC1\_LA15\_P \\ \hline
%IO\_L22N\_T3U\_N7\_DBC\_AD0N\_48 & Y32 & FMC1\_LA15\_N \\ \hline
%IO\_L20P\_T3L\_N2\_AD1P\_48 & W30 & FMC1\_LA16\_P \\ \hline
%IO\_L20N\_T3L\_N3\_AD1N\_48 & Y30 & FMC1\_LA16\_N \\ \hline
%IO\_L13P\_T2L\_N0\_GC\_QBC\_47 & W23 & FMC1\_LA17\_CC\_P \\ \hline
%IO\_L13N\_T2L\_N1\_GC\_QBC\_47 & W24 & FMC1\_LA17\_CC\_N \\ \hline
%IO\_L14P\_T2L\_N2\_GC\_47 & W25 & FMC1\_LA18\_CC\_P \\ \hline
%IO\_L14N\_T2L\_N3\_GC\_47 & Y25 & FMC1\_LA18\_CC\_N \\ \hline
%IO\_L16P\_T2U\_N6\_QBC\_AD3P\_47 & V22 & FMC1\_LA19\_P \\ \hline
%IO\_L16N\_T2U\_N7\_QBC\_AD3N\_47 & V23 & FMC1\_LA19\_N \\ \hline
%IO\_L17P\_T2U\_N8\_AD10P\_47 & T22 & FMC1\_LA20\_P \\ \hline
%IO\_L17N\_T2U\_N9\_AD10N\_47 & T23 & FMC1\_LA20\_N \\ \hline
%IO\_L18P\_T2U\_N10\_AD2P\_47 & V21 & FMC1\_LA21\_P \\ \hline
%IO\_L18N\_T2U\_N11\_AD2N\_47 & W21 & FMC1\_LA21\_N \\ \hline
%IO\_L15P\_T2L\_N4\_AD11P\_47 & U21 & FMC1\_LA22\_P \\ \hline
%IO\_L15N\_T2L\_N5\_AD11N\_47 & U22 & FMC1\_LA22\_N \\ \hline
%IO\_L10P\_T1U\_N6\_QBC\_AD4P\_47 & AB21 & FMC1\_LA23\_P \\ \hline
%IO\_L10N\_T1U\_N7\_QBC\_AD4N\_47 & AC21 & FMC1\_LA23\_N \\ \hline
%IO\_L8P\_T1L\_N2\_AD5P\_47 & AC22 & FMC1\_LA24\_P \\ \hline
%IO\_L8N\_T1L\_N3\_AD5N\_47 & AC23 & FMC1\_LA24\_N \\ \hline
%IO\_L9P\_T1L\_N4\_AD12P\_47 & AA20 & FMC1\_LA25\_P \\ \hline
%IO\_L9N\_T1L\_N5\_AD12N\_47 & AB20 & FMC1\_LA25\_N \\ \hline
%IO\_L7P\_T1L\_N0\_QBC\_AD13P\_47 & AA22 & FMC1\_LA26\_P \\ \hline
%IO\_L7N\_T1L\_N1\_QBC\_AD13N\_47 & AB22 & FMC1\_LA26\_N \\ \hline
%IO\_L6P\_T0U\_N10\_AD6P\_47 & AB25 & FMC1\_LA27\_P \\ \hline
%IO\_L6N\_T0U\_N11\_AD6N\_47 & AB26 & FMC1\_LA27\_N \\ \hline
%IO\_L24P\_T3U\_N10\_47 & V26 & FMC1\_LA28\_P \\ \hline
%IO\_L24N\_T3U\_N11\_47 & W26 & FMC1\_LA28\_N \\ \hline
%IO\_L23P\_T3U\_N8\_47 & V29 & FMC1\_LA29\_P \\ \hline
%IO\_L23N\_T3U\_N9\_47 & W29 & FMC1\_LA29\_N \\ \hline
%IO\_L22P\_T3U\_N6\_DBC\_AD0P\_47 & U26 & FMC1\_LA30\_P \\ \hline
%IO\_L22N\_T3U\_N7\_DBC\_AD0N\_47 & U27 & FMC1\_LA30\_N \\ \hline
%IO\_L21P\_T3L\_N4\_AD8P\_47 & W28 & FMC1\_LA31\_P \\ \hline
%IO\_L21N\_T3L\_N5\_AD8N\_47 & Y28 & FMC1\_LA31\_N \\ \hline
%IO\_L20P\_T3L\_N2\_AD1P\_47 & U24 & FMC1\_LA32\_P \\ \hline
%IO\_L20N\_T3L\_N3\_AD1N\_47 & U25 & FMC1\_LA32\_N \\ \hline
%IO\_L19P\_T3L\_N0\_DBC\_AD9P\_47 & V27 & FMC1\_LA33\_P \\ \hline
%IO\_L19N\_T3L\_N1\_DBC\_AD9N\_47 & V28 & FMC1\_LA33\_N \\ \hline
%VREF\_48 & AA30 & FMC1\_VREF\_A\_M2C \\ \hline
%VREF\_47 & V24 & FMC1\_VREF\_A\_M2C \\ \hline
%
% \end{longtable}
%\end{footnotesize}

%---------------------------------------------------------AMC
\begin{footnotesize}
\begin{longtable}{|p{7cm}|p{1cm}|p{5cm}|}
\hline
\multicolumn{3}{|c|}{\multirow{2}{*}{\textbf{\large{AMC}}}}\\
\multicolumn{3}{|c|}{} \\ \hline
\multicolumn{3}{|c|}{\textbf{\large{FP1}}}\\ \hline
FPGA signal & FPGA ball & Signal on the board \\ \hline
MGTHTXN2\_224 & AL3 & TX4C\_N \\ \hline
MGTHTXP2\_224 & AL4 & TX4C\_P \\ \hline
MGTHRXN2\_224 & AK1 & RX4\_N \\ \hline
MGTHRXP2\_224 & AK2 & RX4\_P \\ \hline
MGTHTXN3\_224 & AK5 & TX5C\_N \\ \hline
MGTHTXP3\_224 & AK6 & TX5C\_P \\ \hline
MGTHRXN3\_224 & AJ3 & RX5\_N \\ \hline
MGTHRXP3\_224 & AJ4 & RX5\_P \\ \hline
IO\_L13N\_T2L\_N1\_GC\_QBC\_45 & AH17 & TXC6\_N \\ \hline
IO\_L13P\_T2L\_N0\_GC\_QBC\_45 & AH18 & TXC6\_P \\ \hline
IO\_L14N\_T2L\_N3\_GC\_45 & AJ16 & RXC6\_N \\ \hline
IO\_L14P\_T2L\_N2\_GC\_45 & AH16 & RXC6\_P \\ \hline
IO\_L6N\_T0U\_N11\_AD6N\_45 & AP15 & TXC7\_N \\ \hline
IO\_L6P\_T0U\_N10\_AD6P\_45 & AP16 & TXC7\_P \\ \hline
IO\_L7N\_T1L\_N1\_QBC\_AD13N\_45 & AM14 & RXC7\_N \\ \hline
IO\_L7P\_T1L\_N0\_QBC\_AD13P\_45 & AL14 & RXC7\_P \\ \hline


%----------------------------------------------------------------------------------------------------------
\multicolumn{3}{|c|}{\textbf{\large{FP2}}}\\ \hline
FPGA signal & FPGA ball & Signal on the board \\ \hline
IO\_L17N\_T2U\_N9\_AD10N\_66 & K12 & TXC8\_N \\ \hline
IO\_L17P\_T2U\_N8\_AD10P\_66 & L12 & TXC8\_P \\ \hline
IO\_L18N\_T2U\_N11\_AD2N\_66 & H13 & RXC8\_N \\ \hline
IO\_L18P\_T2U\_N10\_AD2P\_66 & J13 & RXC8\_P \\ \hline
IO\_L15P\_T2L\_N4\_AD11P\_66 & K11 & TXC9\_N \\ \hline
IO\_L15N\_T2L\_N5\_AD11N\_66 & J11 & TXC9\_P \\ \hline
IO\_L16N\_T2U\_N7\_QBC\_AD3N\_66 & K13 & RXC9\_N \\ \hline
IO\_L16P\_T2U\_N6\_QBC\_AD3P\_66 & L13 & RXC9\_P \\ \hline
IO\_L4N\_T0U\_N7\_DBC\_AD7N\_45 & AN17 & TXC10\_N \\ \hline
IO\_L4P\_T0U\_N6\_DBC\_AD7P\_45 & AN18 & TXC10\_P \\ \hline
IO\_L5N\_T0U\_N9\_AD14N\_45 & AM15 & RXC10\_N \\ \hline
IO\_L5P\_T0U\_N8\_AD14P\_45 & AM16 & RXC10\_P \\ \hline
IO\_L2N\_T0L\_N3\_45 & AP18 & TXC11\_N \\ \hline
IO\_L2P\_T0L\_N2\_45 & AN19 & TXC11\_P \\ \hline
IO\_L3N\_T0L\_N5\_AD15N\_45 & AN16 & RXC11\_N \\ \hline
IO\_L3P\_T0L\_N4\_AD15P\_45 & AM17 & RXC11\_P \\ \hline


%---------------------------------------------------------------------------------------------------------
\multicolumn{3}{|c|}{\textbf{\large{P2P}}}\\ \hline
FPGA signal & FPGA ball & Signal on the board \\ \hline
IO\_L4N\_T0U\_N7\_DBC\_AD7N\_47 & AC27 & TXC12\_N \\ \hline
IO\_L4P\_T0U\_N6\_DBC\_AD7P\_47 & AC26 & TXC12\_P \\ \hline
IO\_L5N\_T0U\_N9\_AD14N\_47 & AB27 & RXC12\_N \\ \hline
IO\_L5P\_T0U\_N8\_AD14P\_47 & AA27 & RXC12\_P \\ \hline
IO\_L2N\_T0L\_N3\_47 & AD26 & TXC13\_N \\ \hline
IO\_L2P\_T0L\_N2\_47 & AD25 & TXC13\_P \\ \hline
IO\_L3N\_T0L\_N5\_AD15N\_47 & AC24 & RXC13\_N \\ \hline
IO\_L3P\_T0L\_N4\_AD15P\_47 & AB24 & RXC13\_P \\ \hline
IO\_L5N\_T0U\_N9\_AD14N\_48 & AE30 & TXC14\_N \\ \hline
IO\_L5P\_T0U\_N8\_AD14P\_48 & AD29 & TXC14\_P \\ \hline
IO\_L6N\_T0U\_N11\_AD6N\_48 & AG30 & RXC14\_N \\ \hline
IO\_L6P\_T0U\_N10\_AD6P\_48 & AF30 & RXC14\_P \\ \hline
IO\_L3N\_T0L\_N5\_AD15N\_48 & AD28 & TXC15\_N \\ \hline
IO\_L3P\_T0L\_N4\_AD15P\_48 & AC28 & TXC15\_P \\ \hline
IO\_L4N\_T0U\_N7\_DBC\_AD7N\_48 & AG29 & RXC15\_N \\ \hline
IO\_L4P\_T0U\_N6\_DBC\_AD7P\_48 & AF29 & RXC15\_P \\ \hline



\end{longtable}
\end{footnotesize}
%---------------------------------------------------------RTM
\begin{footnotesize}
\begin{longtable}{|p{7cm}|p{1cm}|p{5cm}|}
\hline
\multicolumn{3}{|c|}{\multirow{2}{*}{\textbf{\large{RTM}}}}\\
\multicolumn{3}{|c|}{} \\ \hline
FPGA signal & FPGA ball & Signal on the board \\ \hline
MGTHTXP2\_228 & C4 & GTP1TXC\_P \\ \hline
MGTHRXN2\_228 & B1 & GTP1RX\_N \\ \hline
MGTHRXP2\_228 & B2 & GTP1RX\_P \\ \hline
MGTHTXN1\_228 & D5 & GTP2TXC\_N \\ \hline
MGTHTXP1\_228 & D6 & GTP2TXC\_P \\ \hline
MGTHRXN1\_228 & D1 & GTP2RX\_N \\ \hline
MGTHRXP1\_228 & D2 & GTP2RX\_P \\ \hline
MGTHTXN0\_228 & F5 & GTP3TXC\_N \\ \hline
MGTHTXP0\_228 & F6 & GTP3TXC\_P \\ \hline
MGTHRXN0\_228 & E3 & GTP3RX\_N \\ \hline
MGTHRXP0\_228 & E4 & GTP3RX\_P \\ \hline
MGTHTXN3\_227 & G3 & GTP4TXC\_N \\ \hline
MGTHTXP3\_227 & G4 & GTP4TXC\_P \\ \hline
MGTHRXN3\_227 & F1 & GTP4RX\_N \\ \hline
MGTHRXP3\_227 & F2 & GTP4RX\_P \\ \hline
MGTHTXN2\_227 & J3 & GTP5TXC\_N \\ \hline
MGTHTXP2\_227 & J4 & GTP5TXC\_P \\ \hline
MGTHRXN2\_227 & H1 & GTP5RX\_N \\ \hline
MGTHRXP2\_227 & H2 & GTP5RX\_P \\ \hline
MGTHTXN1\_227 & L3 & GTP6TXC\_N \\ \hline
MGTHTXP1\_227 & L4 & GTP6TXC\_P \\ \hline
MGTHRXN1\_227 & K1 & GTP6RX\_N \\ \hline
MGTHRXP1\_227 & K2 & GTP6RX\_P \\ \hline
MGTHTXN0\_227 & N3 & GTP7TXC\_N \\ \hline
MGTHTXP0\_227 & N4 & GTP7TXC\_P \\ \hline
MGTHRXN0\_227 & M1 & GTP7RX\_N \\ \hline
MGTHRXP0\_227 & M2 & GTP7RX\_P \\ \hline
MGTHTXN3\_226 & R3 & GTP8TXC\_N \\ \hline
MGTHTXP3\_226 & R4 & GTP8TXC\_P \\ \hline
MGTHRXN3\_226 & P1 & GTP8RX\_N \\ \hline
MGTHRXP3\_226 & P2 & GTP8RX\_P \\ \hline
MGTHTXN2\_226 & U3 & GTP9TXC\_N \\ \hline
MGTHTXP2\_226 & U4 & GTP9TXC\_P \\ \hline
MGTHRXN2\_226 & T1 & GTP9RX\_N \\ \hline
MGTHRXP2\_226 & T2 & GTP9RX\_P \\ \hline
MGTHTXN1\_226 & W3 & GTP10TXC\_N \\ \hline
MGTHTXP1\_226 & W4 & GTP10TXC\_P \\ \hline
MGTHRXN1\_226 & V1 & GTP10RX\_N \\ \hline
MGTHRXP1\_226 & V2 & GTP10RX\_P \\ \hline
MGTHTXN0\_226 & AA3 & GTP11TXC\_N \\ \hline
MGTHTXP0\_226 & AA4 & GTP11TXC\_P \\ \hline

MGTHTXN3\_225 & AC3 & GTP12TXC\_N \\ \hline
MGTHTXP3\_225 & AC4 & GTP12TXC\_P \\ \hline
MGTHRXN3\_225 & AB1 & GTP12RX\_N \\ \hline
MGTHRXP3\_225 & AB2 & GTP12RX\_P \\ \hline
MGTHTXN2\_225 & AE3 & GTP13TXC\_N \\ \hline
MGTHTXP2\_225 & AE4 & GTP13TXC\_P \\ \hline
MGTHRXN2\_225 & AD1 & GTP13RX\_N \\ \hline
MGTHRXP2\_225 & AD2 & GTP13RX\_P \\ \hline
MGTHTXN1\_225 & AG3 & GTP14TXC\_N \\ \hline
MGTHTXP1\_225 & AG4 & GTP14TXC\_P \\ \hline
MGTHRXN1\_225 & AF1 & GTP14RX\_N \\ \hline
MGTHRXP1\_225 & AF2 & GTP14RX\_P \\ \hline

MGTHTXN0\_225 & AH5 & GTP15TXC\_N \\ \hline
MGTHTXP0\_225 & AH6 & GTP15TXC\_P \\ \hline
MGTHRXN0\_225 & AH1 & GTP15RX\_N \\ \hline
MGTHRXP0\_225 & AH2 & GTP15RX\_P \\ \hline


\end{longtable}
\end{footnotesize}
3 changes: 3 additions & 0 deletions ARTIQ_EE/PCB_Sayma_AMC/Manual/tex/testing.tex
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@@ -0,0 +1,3 @@
\section{Factory acceptance testing}

TBD
36 changes: 36 additions & 0 deletions ARTIQ_EE/PCB_Sayma_AMC/Manual/tex/title.tex
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@@ -0,0 +1,36 @@
\begin{titlepage}




\textcolor{white}{xxx}
\vskip 1 true in

\begin{wrapfigure}{l}{0.01\textwidth}
\begin{center}
\vspace{-35pt}
\includegraphics[scale=0.5]{img/kropki.eps}
\end{center}
\end{wrapfigure}

\textbf{{\LARGE \nazwa}} \\
\linebreak
\textbf{ {\indent \indent \LARGE specification}}\\
\vskip 0.8 true in

\begin{figure}[htbp!]
\centering
\includegraphics[height=10cm]{img/SaymaT.jpg}\\
% \caption{v3.1(02.2017)}
\end{figure}
\begin{center}
v1.0(11.2017)
\end{center}

\vskip 0.7 true in





\end{titlepage}
13 changes: 13 additions & 0 deletions ARTIQ_EE/PCB_Sayma_AMC/Manual/tex/usb-uart.tex
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@@ -0,0 +1,13 @@
\section{USB-UART}
\subsection{UART Switch}

UART from FPGA is connected through Multiplexer (SN74CB3T3257PW). Selection between MMC and USB is preformes automaticly. When micro-USB is connected S siglnal is high and Multiplexer connects USB to FPGA.\\

\subsection{USB-UART bridge}

The USB-UART bridge (FT4232H) requires USB device drivers, vailable free from http://www.ftdichip.com,
which are used to make the FT4232H on the Mini Module appear as a four virtual COM ports (VCP). This
then allows the user to communicate with the USB interface via a standard PC serial emulation port
(TTY).\\ Another FTDI USB driver, the D2XX driver, can also be used with application software to directly
access the FT4232H on the Mini Module though a DLL. \\

26 changes: 26 additions & 0 deletions ARTIQ_EE/PCB_Sayma_AMC/Manual/tex/view.tex
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@@ -0,0 +1,26 @@

\section{Product view}

\begin{figure}[htbp!]
\centering
\includegraphics[height=10cm]{img/SaymaT.jpg}\\
\caption{Top view}
\end{figure}

\begin{figure}[htbp!]
\centering
\includegraphics[height=10cm]{img/SaymaB.jpg}\\
\caption{Bottom view}
\end{figure}

\begin{figure}[htbp!]
\centering
\includegraphics[width=14cm]{img/SaymaF.jpg}\\
\caption{Front view}
\end{figure}

\begin{figure}[htbp!]
\centering
\includegraphics[width=14cm]{img/back.jpg}\\
\caption{Back view}
\end{figure}
153 changes: 153 additions & 0 deletions ARTIQ_EE/PCB_Sayma_AMC/Manual/tex/wiki_sayma.tex
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@@ -0,0 +1,153 @@
\section{Sayma Smart Arbitrary Waveform
Generator}\label{sayma-smart-arbitrary-waveform-generator}

Sayma is a smart arbitrary waveform generator, providing 8 channels of
1.2 GSPS 16-bit DACs (2.4 GHz DAC clock) and 125 MSPS 16-bit ADCs. It
consists of an AMC, providing the high-speed digital logic, and a RTM,
holding the data converters and analog components.

The design files are located in
\href{https://github.com/m-labs/sinara/tree/master/ARTIQ_EE/PCB_Sayma_AMC}{ARTIQ\_EE/PCB\_Sayma\_AMC}
and
\href{https://github.com/m-labs/sinara/tree/master/ARTIQ_EE/PCB_Sayma_RTM}{ARTIQ\_EE/PCB\_Sayma\_RTM}
and, the AMC schematic is
\href{https://github.com/m-labs/sinara/blob/master/ARTIQ_EE/Sayma_AMC.pdf}{here}
and the RTM schematic is
\href{https://github.com/m-labs/sinara/blob/master/ARTIQ_EE/Sayma_RTM.pdf}{here}.
The PCBs are double width, mid height AMC module. Sayma AMC

\subsection{Features}\label{features}

\begin{itemize}

\item
May be used in a uTCA rack or stand-alone operation with fibre-based
DRTIO link
\item
Analog input and output front-ends provided by plug-in
\href{SaymaAFE}{analog front-end modules} (eg BaseMod) for maximum
flexibility.
\item
Extremely flexible \href{SinaraClocking}{clocking options}
\item
Flexible feedback to SAWG parameters planned. Specification
\href{Servo}{here}.
\end{itemize}

\subsection{Key AMC Components}\label{key-amc-components}

\begin{itemize}

\item
\textbf{FPGA}: XCKU040-1FFVA1156C Kintex Ultrascale, 520 I/O, 530K
Logic Cells, Speed Grade 1, 20 GTH transceivers (up to 16.3 Gb/s) --
motivation for this FPGA choice is
\href{https://github.com/m-labs/sinara/wiki/artiq_hardware\#recommendation}{here}
\item
\textbf{DRAM}: MT41K256M16TW-107:P, DDR3, 32 MB x 16 x 8 banks = 4 GB
\item
\textbf{clock recovery}: Si5324 is a precision clock multiplier and
jitter attenuator
\end{itemize}

\subsection{Key RTM Components}\label{key-rtm-components}

\begin{itemize}

\item
\textbf{DAC}: AD9154 4-channel high-speed data converter

\begin{itemize}

\item
data rate is 1.2 GS/s at 16-bit
\item
clock is up to 2.4 GHz (1x, 2x, 4x and 8x interpolating modes)
\item
supports mix-mode to emphasize power in 3rd Nyquist Zone
\item
interface is 8-lane JESD204B (subclass 1)
\item
power consumption is 2.11 W
\item
each Sayma has 2 AD9154
\end{itemize}
\item
\textbf{ADC}: AD9656 is a 4-channel high-speed digitizer

\begin{itemize}

\item
data rate is 125 MS/s at 16-bit
\item
clock is up to 125 MHz
\item
650 MHz analog bandwidth
\item
interface is 8-lane, 8 Gb/s per lane, JESD204B (subclass 1)
\item
each Sayma has 2 AD9656
\end{itemize}
\item
\textbf{clock generation}: (summarized \href{SinaraClocking}{here})

\begin{itemize}

\item
Sayma has several distinct clock domains

\begin{itemize}

\item
DAC, JESB204B output clock
\item
ADC, JESD204B input clock
\item
LO for analog mezzanines
\end{itemize}
\item
These clocks may be generated using a low phase noise
\href{ClockMezzanines}{Clock Mezzanine} PCB. A single Clock
Mezzanine can be shared by several Sayma in a uTCA crate using
{[}Baikal{]} PCB and an RTM RF backplane. Alternately, each Sayma
can have its own distinct Clock Mezzanine (local generation).
\end{itemize}
\item
\textbf{clock distribution}

\begin{itemize}

\item
HMC7043 SPI 14-Output Fanout Buffer for JESD204B
\item
HMC830 SPI fractional-N PLL
\end{itemize}
\item
\textbf{calibration ADC}: AD7194BCPZ is a 20-bit ADC for
monitoring/calibration
\end{itemize}

\subsection{Transceiver/connector
usage}\label{transceiverconnector-usage}

\begin{itemize}

\item
SFP1: DRTIO downstream
\item
SFP2: DRTIO downstream
\item
SATA1: DRTIO upstream (different bitstream probably)
\item
SATA2 (swapped): DRTIO downstream
\item
FAT\_PIPE1 (FABRICD): DRTIO upstream
\item
FAT\_PIPE2 (FABRICE): not used
\item
FMC:
\item
LA: FMC DIO32: TTL IO
\end{itemize}


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\section{Overview}\label{overview}

MicroTCA (uTCA) is Sinara's preferred form-factor for hardware with
high-speed data converters requiring deterministic phase control, such
as the \href{Sayma}{\emph{Sayma}} 2.4 GSPS smart arbitrary waveform
generator (SAWG).

uTCA is a modular, open standard originally developed by the
telecommunications industry. It allows a single rack master -- the Micro
TCA Carrier Hub (MCH) -- to control multiple slave boards, known as
Advanced Mezzanine Cards (AMCs) via a high-speed digital backplane. uTCA
chassis and backplanes are available commercially of the shelf (COTS).

We make use of the most recent extension to the uTCA standard, uTCA.4.
Originating in the high-energy and particle physics (HEPP) community,
uTCA.4 introduces rear-transition modules (RTMs) along with a second
backplane for low-noise RF signals (RFBP). Each RTM connects to an AMC
(one RTM per AMC). Typically, the AMCs hold FPGAs and other high-speed
digital hardware, communicating with the MCH via gigabit serial links
over the AMC backplane. The RTMs hold data converters and other
low-noise analog components, controlled by the corresponding AMC. The
RFBP provides low-noise clocks and local oscillators (LOs). The RTMs and
RFBP are screened from the AMCs to minimise interference from the
high-speed digital logic.

\begin{figure}[htbp!]
\centering
\includegraphics[width=15cm]{img/MTCA_Front.jpg}
\caption{Micro TCA chassis with 3 Sayma AMC modules inserted}
\end{figure}

(above) Micro TCA chassis with 3 Sayma AMC modules inserted.

Micro TCA chassis with 4 RTM modules inserted. One of them with 4
BaseMod AFE mezzanines installed.

\begin{figure}[htbp!]
\centering
\includegraphics[width=15cm]{img/MTCA_Back.jpg}
\caption{Micro TCA chassis with 4 RTM modules inserted. One of them has
4 BaseMod AFE mezzanines installed.}
\end{figure}

\section{uTCA.4 RF Backplane}\label{utca.4-rf-backplane}

\href{http://mtca.desy.de/sites/site_mtca/content/e172206/e205636/e212584/e248086/uRFB_concept_Datasheet_19.12.2014_eng.pdf}{RF
BP datasheet}
\href{http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=7097413\&tag=1}{RF
BP measurements}

\section{uTCA in Sinara}\label{utca-in-sinara}

\href{Metlino}{\emph{Metlino}} has been developed as an MCH optimised
for use in Sinara. It can either be the ARTIQ master or a slave,
connected to the master via DRTIO.

uTCA hardware interfaces with the extension modules either directly,
using a \href{VHDCICarrier}{VHDCI carrier}, or indirectly, using a Kasli
DRTIO slave.

To do: * Some images to illustrate what uTCA systems look like * Explain
how Baikal etc fit in * Add BP schematics that show what the
connectivity is * Any more useful information?

\section{uTCA parts and suppliers}\label{utca-parts-and-suppliers}

Add parts and suppliers from the issues list\ldots{}

\section{Schematic / Layout Viewer}\label{schematic-layout-viewer}

Mentor has a free tool called
\href{https://www.mentor.com/pcb/downloads/visecad-viewer/}{visECAD
Viewer}.

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