atlys: request 128 bits dram port for encoder (should fix issue)

timvideos · Jan 21, 2018 · aa201c6 · aa201c6
1 parent e423776
commit aa201c6
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Showing 2 changed files with 2 additions and 2 deletions.
diff --git a/gateware/encoder/core.py b/gateware/encoder/core.py
@@ -29,7 +29,7 @@ def __init__(self, dram_port):
         burst_pixels = dram_port.dw//pixel_bits
         alignment_bits = bits_for(dram_port.dw//8) - 1
 
-        self.comb += dma.source.connect(source) # XXX add Converter
+        self.comb += dma.source.connect(source)
 
         base = Signal(32)
         h_width = self.h_width.storage

diff --git a/targets/atlys/hdmi2usb.py b/targets/atlys/hdmi2usb.py
@@ -23,7 +23,7 @@ class HDMI2USBSoC(BaseSoC):
     def __init__(self, platform, *args, **kwargs):
         BaseSoC.__init__(self, platform, *args, **kwargs)
 
-        encoder_port = self.sdram.crossbar.get_port()
+        encoder_port = self.sdram.crossbar.get_port(mode="read", dw=128)
         self.submodules.encoder_reader = EncoderDMAReader(encoder_port)
         encoder_cdc = stream.AsyncFIFO([("data", 128)], 4)
         encoder_cdc = ClockDomainsRenamer({"write": "sys",