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vhdl work "Urukul_CPLD.vhd" | ||
vhdl work "Urukul_CPLD.vhd" |
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ARTIQ_ALTIUM/EEMs/Urukul/CPLD_code/Urukul_CPLD/Urukul_CPLD.vhd
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DDS_Profile=P0,P1,P2 | ||
DDS_Profile=P0,P1,P2 |
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DDS_Profile=P2,P1,P0 | ||
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ARTIQ_ALTIUM/EEMs/Urukul/Project Outputs for PCB_3U_DDS/PCB_3U_DDS_9910.PDF
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ARTIQ_ALTIUM/EEMs/Urukul/Project Outputs for PCB_3U_DDS/PCB_3U_DDS_9912.PDF
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ARTIQ_ALTIUM/EEMs/Urukul/PCB_3U_DDS.PcbDoc → ARTIQ_ALTIUM/EEMs/Urukul/Urukul.PcbDoc
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