Skip to content

Commit 0f05a1c

Browse files
committedJan 30, 2018
Kasli v1.1rc3
Clock recovery: Switched balun and DNPed C9 and C13 FPGAPower&Misc: Removed C49 and connected VREFN with VREFP PowerSupplies: no real changes Schlib1: Added TC2-1TX+ USB_Serial_Quad: Moved I2C_SW_RESET to BDBUS5 PCB: Everything above + connected shielding vias to GND planes on all layers
1 parent 327ecdd commit 0f05a1c

8 files changed

+633
-40
lines changed
 

Diff for: ‎ARTIQ_ALTIUM/Kasli/PCB_Kasli/ClockRecovery.SchDoc

-14 KB
Binary file not shown.

Diff for: ‎ARTIQ_ALTIUM/Kasli/PCB_Kasli/FPGAPower&Misc.SchDoc

-7.5 KB
Binary file not shown.

Diff for: ‎ARTIQ_ALTIUM/Kasli/PCB_Kasli/PCB_3U_Kasli.PrjPCB

+633-40
Large diffs are not rendered by default.
0 Bytes
Binary file not shown.

Diff for: ‎ARTIQ_ALTIUM/Kasli/PCB_Kasli/PCB_Kasli.PCBDOC

-383 KB
Binary file not shown.

Diff for: ‎ARTIQ_ALTIUM/Kasli/PCB_Kasli/PowerSupplies.SchDoc

0 Bytes
Binary file not shown.

Diff for: ‎ARTIQ_ALTIUM/Kasli/PCB_Kasli/Schlib1.SchLib

7 KB
Binary file not shown.

Diff for: ‎ARTIQ_ALTIUM/Kasli/PCB_Kasli/USB_Serial_Quad.SchDoc

0 Bytes
Binary file not shown.

0 commit comments

Comments
 (0)