targets: update artix 7 ddr phy parameters

timvideos · Jan 15, 2018 · 1be967a · 1be967a
1 parent 9aea390
commit 1be967a
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Showing 4 changed files with 8 additions and 8 deletions.
diff --git a/targets/arty/base.py b/targets/arty/base.py
@@ -148,8 +148,8 @@ def __init__(self, platform, spiflash="spiflash_1x", **kwargs):
         sdram_module = MT41K128M16(self.clk_freq, "1:4")
         self.submodules.ddrphy = a7ddrphy.A7DDRPHY(
             platform.request("ddram"))
-        self.add_constant("A7DDRPHY_BITSLIP", 2)
-        self.add_constant("A7DDRPHY_DELAY", 6)
+        self.add_constant("READ_LEVELING_BITSLIP", 2)
+        self.add_constant("READ_LEVELING_DELAY", 6)
         controller_settings = ControllerSettings(
             with_bandwidth=True,
             cmd_buffer_depth=8,

diff --git a/targets/netv2/base.py b/targets/netv2/base.py
@@ -108,8 +108,8 @@ def __init__(self, platform, **kwargs):
         sdram_module = MT41J128M16(self.clk_freq, "1:4")
         self.submodules.ddrphy = a7ddrphy.A7DDRPHY(
             platform.request("ddram"))
-        self.add_constant("A7DDRPHY_BITSLIP", 2)
-        self.add_constant("A7DDRPHY_DELAY", 8)
+        self.add_constant("READ_LEVELING_BITSLIP", 2)
+        self.add_constant("READ_LEVELING_DELAY", 8)
         controller_settings = ControllerSettings(
             with_bandwidth=True,
             cmd_buffer_depth=8,

diff --git a/targets/netv2/bridge_uart.py b/targets/netv2/bridge_uart.py
@@ -126,8 +126,8 @@ def __init__(self, platform, **kwargs):
 
         # sdram
         self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram"))
-        self.add_constant("A7DDRPHY_BITSLIP", 2)
-        self.add_constant("A7DDRPHY_DELAY", 8)
+        self.add_constant("READ_LEVELING_BITSLIP", 2)
+        self.add_constant("READ_LEVELING_DELAY", 8)
         sdram_module = MT41J128M16(self.clk_freq, "1:4")
         self.register_sdram(self.ddrphy,
                             sdram_module.geom_settings,

diff --git a/targets/nexys_video/base.py b/targets/nexys_video/base.py
@@ -127,8 +127,8 @@ def __init__(self, platform, spiflash="spiflash_1x", **kwargs):
 
         # sdram
         self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram"))
-        self.add_constant("A7DDRPHY_BITSLIP", 3)
-        self.add_constant("A7DDRPHY_DELAY", 14)
+        self.add_constant("READ_LEVELING_BITSLIP", 3)
+        self.add_constant("READ_LEVELING_DELAY", 14)
         sdram_module = MT41K256M16(self.clk_freq, "1:4")
         self.register_sdram(self.ddrphy,
                             sdram_module.geom_settings,