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base repository: m-labs/artiq
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head repository: m-labs/artiq
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compare: 0b6739663066
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  • 2 commits
  • 2 files changed
  • 1 contributor

Commits on Jan 25, 2017

  1. Copy the full SHA
    57f54db View commit details
  2. test: convert test_pulse_rate_dds to use mu.

    Before this commit, this test was actually measuring soft-FP
    performance.
    whitequark committed Jan 25, 2017
    Copy the full SHA
    0b67396 View commit details
Showing with 8 additions and 3 deletions.
  1. +4 −0 artiq/compiler/transforms/llvm_ir_generator.py
  2. +4 −3 artiq/test/coredevice/test_rtio.py
4 changes: 4 additions & 0 deletions artiq/compiler/transforms/llvm_ir_generator.py
Original file line number Diff line number Diff line change
@@ -532,6 +532,10 @@ def process_function(self, func):
if func.is_cold:
self.llfunction.attributes.add('cold')
self.llfunction.attributes.add('noinline')
if 'inline' in func.flags:
self.llfunction.attributes.add('inlinehint')
if 'forceinline' in func.flags:
self.llfunction.attributes.add('alwaysinline')

self.llfunction.attributes.add('uwtable')
self.llfunction.attributes.personality = self.llbuiltin("__artiq_personality")
7 changes: 4 additions & 3 deletions artiq/test/coredevice/test_rtio.py
Original file line number Diff line number Diff line change
@@ -119,13 +119,14 @@ def build(self):
def run(self):
self.core.reset()
dt = self.core.seconds_to_mu(5*us)
freq = self.core_dds.frequency_to_ftw(100*MHz)
while True:
delay(10*ms)
for i in range(1250):
try:
with self.core_dds.batch:
self.dds0.set(100*MHz)
self.dds1.set(100*MHz)
self.dds0.set_mu(freq)
self.dds1.set_mu(freq)
delay_mu(dt)
except RTIOUnderflow:
dt += 100
@@ -360,7 +361,7 @@ def test_pulse_rate_dds(self):
rate = self.dataset_mgr.get("pulse_rate")
print(rate)
self.assertGreater(rate, 1*us)
self.assertLess(rate, 6.2*us)
self.assertLess(rate, 6.5*us)

def test_loopback_count(self):
npulses = 2