tests: Fixed incorrect truth table in Luts HiL test. Fixed incorrect LUT truth table in GP_2LUT example code

azonenberg · azonenberg · commit 691962d09160 · 2016-12-31T10:31:44.000-08:00
diff --git a/doc/gp4-hdl.tex b/doc/gp4-hdl.tex
@@ -986,7 +986,7 @@ \subsubsection{Verilog Usage Example}
 wire b;
 wire o;
 GP_2LUT #(
-	.INIT(4'h4)
+	.INIT(4'h8)
 ) lut(
 	.IN0(a),
 	.IN1(b),
diff --git a/tests/greenpak4/slg46620v/Luts.v b/tests/greenpak4/slg46620v/Luts.v
@@ -43,7 +43,7 @@ module Luts(din, dout_instantiated, dout_inferred);
 
 	GP_INV inv_inst (
 		.IN(din[0]), .OUT(dout_instantiated[0]));
-	GP_2LUT #(.INIT(4'hB)) lut2_inst (
+	GP_2LUT #(.INIT(4'h7)) lut2_inst (
 		.IN0(din[0]), .IN1(din[1]), .OUT(dout_instantiated[1]));
 	GP_3LUT #(.INIT(8'h7F)) lut3_inst (
 		.IN0(din[0]), .IN1(din[1]), .IN2(din[2]), .OUT(dout_instantiated[2]));
