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integration: add missing newlines.
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whitequark committed Dec 31, 2016
1 parent a05121a commit c26f7cf
Showing 1 changed file with 2 additions and 2 deletions.
4 changes: 2 additions & 2 deletions misoc/integration/cpu_interface.py
Original file line number Diff line number Diff line change
@@ -47,7 +47,7 @@ def get_mem_header(regions, flash_boot_address):
def get_mem_rust(regions, flash_boot_address):
r = "// Include this file as:\n"
r += "// include!(concat!(env!(\"BUILDINC_DIRECTORY\"), \"/generated/mem.rs\"));\n"
r += "#[allow(dead_code)]"
r += "#[allow(dead_code)]\n"
r += "pub mod mem {\n"
for name, base, size in regions:
r += " pub const {name}_BASE: usize = 0x{base:08x};\n". \
@@ -188,7 +188,7 @@ def _get_rw_functions_rs(reg_name, reg_base, nwords, busword, read_only):
def get_csr_rust(regions, constants, with_access_functions=True):
r = "// Include this file as:\n"
r += "// include!(concat!(env!(\"BUILDINC_DIRECTORY\"), \"/generated/csr.rs\"));\n"
r += "#[allow(dead_code)]"
r += "#[allow(dead_code)]\n"
r += "pub mod csr {\n"

for name, origin, busword, obj in regions:

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