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base repository: m-labs/artiq
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head repository: m-labs/artiq
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compare: 26e7f68b5dbd
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  • 3 commits
  • 10 files changed
  • 1 contributor

Commits on Jan 1, 2017

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    a3041fb View commit details
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    bb056c1 View commit details
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    26e7f68 View commit details
17 changes: 9 additions & 8 deletions artiq/firmware/libboard/ad9154.rs
Original file line number Diff line number Diff line change
@@ -1,5 +1,6 @@
use csr;
use ad9154_reg::reg;
use clock;
mod ad9154_reg;

fn spi_setup() {
unsafe {
@@ -133,13 +134,13 @@ fn dac_setup() -> Result<(), &'static str> {
0*ad9154_reg::LSBFIRST_M | 0*ad9154_reg::LSBFIRST |
0*ad9154_reg::ADDRINC_M | 0*ad9154_reg::ADDRINC |
1*ad9154_reg::SDOACTIVE_M | 1*ad9154_reg::SDOACTIVE);
busywait_us(100);
clock::spin_us(100);
write(ad9154_reg::SPI_INTFCONFA,
0*ad9154_reg::SOFTRESET_M | 0*ad9154_reg::SOFTRESET |
0*ad9154_reg::LSBFIRST_M | 0*ad9154_reg::LSBFIRST |
0*ad9154_reg::ADDRINC_M | 0*ad9154_reg::ADDRINC |
1*ad9154_reg::SDOACTIVE_M | 1*ad9154_reg::SDOACTIVE);
busywait_us(100);
clock::spin_us(100);
if read(ad9154_reg::PRODIDH) as u16 << 8 |
read(ad9154_reg::PRODIDL) as u16 != 0x9154 {
return Err("AD9154 not found")
@@ -149,7 +150,7 @@ fn dac_setup() -> Result<(), &'static str> {
0*ad9154_reg::PD_DAC0 | 0*ad9154_reg::PD_DAC1 |
0*ad9154_reg::PD_DAC2 | 0*ad9154_reg::PD_DAC3 |
0*ad9154_reg::PD_BG);
busywait_us(100);
clock::spin_us(100);
write(ad9154_reg::TXENMASK1, 0*ad9154_reg::DACA_MASK |
0*ad9154_reg::DACB_MASK); // TX not controlled by TXEN pins
write(ad9154_reg::CLKCFG0,
@@ -348,7 +349,7 @@ fn dac_setup() -> Result<(), &'static str> {
0x9*ad9154_reg::SYNCMODE | 1*ad9154_reg::SYNCENABLE |
1*ad9154_reg::SYNCARM | 0*ad9154_reg::SYNCCLRSTKY |
0*ad9154_reg::SYNCCLRLAST);
busywait_us(1000); // ensure at least one sysref edge
clock::spin_us(1000); // ensure at least one sysref edge
if read(ad9154_reg::SYNC_STATUS) & ad9154_reg::SYNC_LOCK == 0:
return Err("no sync lock")
write(ad9154_reg::XBAR_LN_0_1,
@@ -413,15 +414,15 @@ fn cfg() -> Result<(), &'static str> {
jesd_enable(false);
jesd_prbs(false);
jesd_stpl(false);
busywait_us(10000);
clock::spin_us(10000);
jesd_enable(true);
dac_setup();
jesd_enable(false);
busywait_us(10000);
clock::spin_us(10000);
jesd_enable(true);
monitor();
while !jesd_ready() {}
busywait_us(10000);
clock::spin_us(10000);
if read(ad9154_reg::CODEGRPSYNCFLG) != 0x0f {
return Err("bad CODEGRPSYNCFLG")
}
2 changes: 1 addition & 1 deletion artiq/firmware/libboard/ad9516.rs
Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
use csr;
use ad9516_reg::reg;
mod ad9516_reg;

fn spi_setup() {
unsafe {
Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
use board::csr;
use csr;

const INIT: u64 = ::core::i64::MAX as u64;
const FREQ: u64 = csr::CONFIG_CLOCK_FREQUENCY as u64;
1 change: 1 addition & 0 deletions artiq/firmware/libboard/lib.rs
Original file line number Diff line number Diff line change
@@ -7,6 +7,7 @@ include!(concat!(env!("BUILDINC_DIRECTORY"), "/generated/mem.rs"));
include!(concat!(env!("BUILDINC_DIRECTORY"), "/generated/csr.rs"));
pub mod spr;
pub mod irq;
pub mod clock;

extern {
pub fn flush_cpu_dcache();
11 changes: 5 additions & 6 deletions artiq/firmware/runtime/lib.rs
Original file line number Diff line number Diff line change
@@ -58,7 +58,6 @@ pub extern fn panic_fmt(args: self::core::fmt::Arguments, file: &'static str, li
}

mod config;
mod clock;
mod rtio_mgt;
mod mailbox;
mod rpc_queue;
@@ -102,14 +101,14 @@ pub unsafe extern fn rust_main() {
static mut LOG_BUFFER: [u8; 65536] = [0; 65536];
BufferLogger::new(&mut LOG_BUFFER[..])
.register(move || {
clock::init();
board::clock::init();
info!("booting ARTIQ");
info!("software version {}", GIT_COMMIT);
info!("gateware version {}", board::ident(&mut [0; 64]));

let t = clock::get_ms();
let t = board::clock::get_ms();
info!("press 'e' to erase startup and idle kernels...");
while clock::get_ms() < t + 1000 {
while board::clock::get_ms() < t + 1000 {
if readchar_nonblock() != 0 && readchar() == b'e' as libc::c_char {
config::remove("startup_kernel");
config::remove("idle_kernel");
@@ -149,10 +148,10 @@ pub unsafe extern fn isr() {

#[no_mangle]
pub fn sys_now() -> u32 {
clock::get_ms() as u32
board::clock::get_ms() as u32
}

#[no_mangle]
pub fn sys_jiffies() -> u32 {
clock::get_ms() as u32
board::clock::get_ms() as u32
}
6 changes: 3 additions & 3 deletions artiq/firmware/runtime/logger.rs
Original file line number Diff line number Diff line change
@@ -2,7 +2,7 @@ use core::{mem, ptr};
use core::cell::{Cell, RefCell};
use log::{self, Log, LogLevel, LogMetadata, LogRecord, LogLevelFilter};
use log_buffer::LogBuffer;
use clock;
use board;

pub struct BufferLogger {
buffer: RefCell<LogBuffer<&'static mut [u8]>>,
@@ -70,13 +70,13 @@ impl Log for BufferLogger {
use core::fmt::Write;
writeln!(self.buffer.borrow_mut(),
"[{:12}us] {:>5}({}): {}",
clock::get_us(), record.level(), record.target(), record.args()).unwrap();
board::clock::get_us(), record.level(), record.target(), record.args()).unwrap();

// Printing to UART is really slow, so avoid doing that when we have an alternative
// route to retrieve the debug messages.
if self.trace_to_uart.get() || record.level() <= LogLevel::Info {
println!("[{:12}us] {:>5}({}): {}",
clock::get_us(), record.level(), record.target(), record.args());
board::clock::get_us(), record.level(), record.target(), record.args());
}
}
}
3 changes: 1 addition & 2 deletions artiq/firmware/runtime/rtio_mgt.rs
Original file line number Diff line number Diff line change
@@ -4,8 +4,7 @@ use sched::Scheduler;

#[cfg(has_rtio_crg)]
pub mod crg {
use clock;
use board::csr;
use board::{clock, csr};

pub fn init() {
unsafe { csr::rtio_crg::pll_reset_write(0) }
6 changes: 3 additions & 3 deletions artiq/firmware/runtime/sched.rs
Original file line number Diff line number Diff line change
@@ -6,7 +6,7 @@ use std::io::{Read, Write, Result, Error, ErrorKind};
use fringe::OwnedStack;
use fringe::generator::{Generator, Yielder, State as GeneratorState};
use lwip;
use clock;
use board;
use urc::Urc;

#[derive(Debug)]
@@ -106,7 +106,7 @@ impl Scheduler {

if self.threads.len() == 0 { return }

let now = clock::get_ms();
let now = board::clock::get_ms();

let start_index = self.index;
loop {
@@ -216,7 +216,7 @@ pub struct Waiter<'a>(&'a Yielder<WaitResult, WaitRequest, OwnedStack>);
impl<'a> Waiter<'a> {
pub fn sleep(&self, duration_ms: u64) -> Result<()> {
let request = WaitRequest {
timeout: Some(clock::get_ms() + duration_ms),
timeout: Some(board::clock::get_ms() + duration_ms),
event: None
};

6 changes: 3 additions & 3 deletions artiq/firmware/runtime/session.rs
Original file line number Diff line number Diff line change
@@ -3,7 +3,7 @@ use std::{mem, str};
use std::cell::RefCell;
use std::io::{self, Read, Write, BufWriter};
use std::btree_set::BTreeSet;
use {config, rtio_mgt, clock, mailbox, rpc_queue, kernel};
use {config, rtio_mgt, mailbox, rpc_queue, kernel};
use logger::BufferLogger;
use cache::Cache;
use urc::Urc;
@@ -58,7 +58,7 @@ enum KernelState {
struct Session<'a> {
congress: &'a mut Congress,
kernel_state: KernelState,
watchdog_set: clock::WatchdogSet,
watchdog_set: board::clock::WatchdogSet,
log_buffer: String,
interner: BTreeSet<String>
}
@@ -68,7 +68,7 @@ impl<'a> Session<'a> {
Session {
congress: congress,
kernel_state: KernelState::Absent,
watchdog_set: clock::WatchdogSet::new(),
watchdog_set: board::clock::WatchdogSet::new(),
log_buffer: String::new(),
interner: BTreeSet::new()
}
1 change: 0 additions & 1 deletion doc/manual/installing_from_source.rst
Original file line number Diff line number Diff line change
@@ -63,7 +63,6 @@ and the ARTIQ kernels.
$ cd ~/artiq-dev
$ git clone -b artiq-1.16.0 https://github.com/m-labs/rust
$ cd rust
$ git checkout artiq
$ git submodule update --init
$ mkdir build
$ cd build