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base repository: m-labs/artiq
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head repository: m-labs/artiq
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compare: d3dfbdfa8c41
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  • 2 commits
  • 2 files changed
  • 1 contributor

Commits on Jan 13, 2017

  1. Copy the full SHA
    0edffb5 View commit details
  2. typo

    sbourdeauducq committed Jan 13, 2017
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    d3dfbdf View commit details
Showing with 2 additions and 2 deletions.
  1. +1 −1 README_PHASER.rst
  2. +1 −1 artiq/gateware/drtio/rt_packets.py
2 changes: 1 addition & 1 deletion README_PHASER.rst
Original file line number Diff line number Diff line change
@@ -89,7 +89,7 @@ Setup
* Refer to the ARTIQ documentation to configure an IP address and other settings for the transmitter device.
If the board was running stock ARTIQ before, the settings will be kept.
* A 300 MHz clock of roughly 10 dBm (0.2 to 3.4 V peak-to-peak into 50 Ohm) must be connected to the AD9154-FMC-EBZ J1. The input is 50 Ohm terminated. The RTIO clock, DAC deviceclock, FPGA deviceclock, and SYSREF are derived from this signal.
* Configure an oscilliscope to trigger at 0.5 V on rising edge of ttl_sma (user_gpio_n on the KC705 board). Monitor DAC0 (J17) on the oscilloscope set for 100 mV/div and 200 ns/div.
* Configure an oscilloscope to trigger at 0.5 V on rising edge of ttl_sma (user_gpio_n on the KC705 board). Monitor DAC0 (J17) on the oscilloscope set for 100 mV/div and 200 ns/div.
* An example device database, several status and test scripts are provided in ``artiq/examples/phaser/``. ::

cd artiq/examples/phaser
2 changes: 1 addition & 1 deletion artiq/gateware/drtio/rt_packets.py
Original file line number Diff line number Diff line change
@@ -297,7 +297,7 @@ def __init__(self, link_layer):

ongoing_packet_next = Signal()
ongoing_packet = Signal()
self.sync.rtio_rx += ongoing_packet.eq(ongoing_packet_next)
self.sync += ongoing_packet.eq(ongoing_packet_next)

rx_fsm.act("INPUT",
If(rx_dp.frame_r,