m-labs · Jan 10, 2017 · Jan 10, 2017 · Jan 10, 2017 · Jan 10, 2017 · Jan 10, 2017
Showing with 32 additions and 45 deletions.

+1 −1 artiq/firmware/runtime/lib.rs

+21 −23 artiq/firmware/runtime/rtio_mgt.rs

+4 −10 artiq/gateware/drtio/rt_controller.py

+1 −1 artiq/gateware/targets/kc705_drtio_satellite.py

+5 −10 artiq/test/gateware/drtio/test_full_stack.py
diff --git a/artiq/firmware/runtime/lib.rs b/artiq/firmware/runtime/lib.rs
@@ -129,7 +129,7 @@ pub unsafe extern fn rust_main() {
         network_init();
 
         let mut scheduler = sched::Scheduler::new();
-        rtio_mgt::startup(&scheduler);
+        rtio_mgt::startup(scheduler.spawner());
         scheduler.spawner().spawn(16384, session::thread);
         #[cfg(has_rtio_moninj)]
         scheduler.spawner().spawn(4096, moninj::thread);

diff --git a/artiq/firmware/runtime/rtio_mgt.rs b/artiq/firmware/runtime/rtio_mgt.rs
@@ -1,6 +1,6 @@
 use config;
 use board::csr;
-use sched::Scheduler;
+use sched::Spawner;
 
 #[cfg(has_rtio_crg)]
 pub mod crg {
@@ -39,11 +39,11 @@ pub mod crg {
 #[cfg(has_drtio)]
 mod drtio {
     use board::csr;
-    use sched::{Scheduler, Waiter, Spawner};
+    use sched::{Waiter, Spawner};
 
-    pub fn startup(scheduler: &Scheduler) {
-        scheduler.spawner().spawn(4096, link_thread);
-        scheduler.spawner().spawn(4096, error_thread);
+    pub fn startup(spawner: &Spawner) {
+        spawner.spawn(4096, link_thread);
+        spawner.spawn(4096, error_thread);
     }
 
     fn link_is_up() -> bool {
@@ -110,38 +110,36 @@ mod drtio {
         }
     }
 
-    fn packet_error_present() -> bool {
+    fn poll_errors() -> bool {
         unsafe {
-            csr::drtio::packet_err_present_read() != 0
-        }
-    }
-
-    fn get_packet_error() -> u8 {
-        unsafe {
-            let err = csr::drtio::packet_err_code_read();
-            csr::drtio::packet_err_present_write(1);
-            err
+            if csr::drtio::packet_err_present_read() != 0 {
+                error!("packet error {}", csr::drtio::packet_err_code_read());
+                csr::drtio::packet_err_present_write(1)
+            }
+            if csr::drtio::o_fifo_space_timeout_read() != 0 {
+                error!("timeout attempting to get remote FIFO space");
+                csr::drtio::o_fifo_space_timeout_write(1)
+            }
         }
+        false
     }
 
     pub fn error_thread(waiter: Waiter, _spawner: Spawner) {
-        loop {
-            waiter.until(packet_error_present).unwrap();
-            error!("DRTIO packet error {}", get_packet_error());
-        }
+        // HACK
+        waiter.until(poll_errors).unwrap();
     }
 
 }
 
 #[cfg(not(has_drtio))]
 mod drtio {
-    use sched::Scheduler;
+    use sched::Spawner;
 
-    pub fn startup(_scheduler: &Scheduler) {}
+    pub fn startup(_spawner: &Spawner) {}
     pub fn init() {}
 }
 
-pub fn startup(scheduler: &Scheduler) {
+pub fn startup(spawner: &Spawner) {
     crg::init();
 
     let mut opt = [b'i'];
@@ -167,7 +165,7 @@ pub fn startup(scheduler: &Scheduler) {
         warn!("fix clocking and reset the device");
     }
 
-    drtio::startup(scheduler);
+    drtio::startup(spawner);
     init_core()
 }
 

diff --git a/artiq/gateware/drtio/rt_controller.py b/artiq/gateware/drtio/rt_controller.py
@@ -139,8 +139,6 @@ def __init__(self, rt_packets, channel_count, fine_ts_width):
         cond_sequence_error = self.cri.o_timestamp < last_timestamps.dat_r
         cond_underflow = ((self.cri.o_timestamp[fine_ts_width:]
                            - self.csrs.underflow_margin.storage[fine_ts_width:]) < self.counter.value_sys)
-        cond_fifo_emptied = ((last_timestamps.dat_r[fine_ts_width:] < self.counter.value_sys)
-                             & (last_timestamps.dat_r != 0))
 
         fsm.act("IDLE",
             If(self.cri.cmd == cri.commands["write"],
@@ -161,13 +159,9 @@ def __init__(self, rt_packets, channel_count, fine_ts_width):
             rt_packets.write_stb.eq(1),
             If(rt_packets.write_ack,
                 fifo_spaces.we.eq(1),
-                If(cond_fifo_emptied,
-                    fifo_spaces.dat_w.eq(1),
-                ).Else(
-                    fifo_spaces.dat_w.eq(fifo_spaces.dat_r - 1)
-                ),
+                fifo_spaces.dat_w.eq(fifo_spaces.dat_r - 1),
                 last_timestamps.we.eq(1),
-                If(~cond_fifo_emptied & (fifo_spaces.dat_r <= 1),
+                If(fifo_spaces.dat_r <= 1,
                     NextState("GET_FIFO_SPACE")
                 ).Else(
                     NextState("IDLE")
@@ -189,7 +183,7 @@ def __init__(self, rt_packets, channel_count, fine_ts_width):
             fifo_spaces.we.eq(1),
             rt_packets.fifo_space_not_ack.eq(1),
             If(rt_packets.fifo_space_not,
-                If(rt_packets.fifo_space > 0,
+                If(rt_packets.fifo_space != 0,
                     NextState("IDLE")
                 ).Else(
                     NextState("GET_FIFO_SPACE")
@@ -198,7 +192,7 @@ def __init__(self, rt_packets, channel_count, fine_ts_width):
             timeout_counter.wait.eq(1),
             If(timeout_counter.done,
                 signal_fifo_space_timeout.eq(1),
-                NextState("IDLE")
+                NextState("GET_FIFO_SPACE")
             )
         )
 

diff --git a/artiq/gateware/targets/kc705_drtio_satellite.py b/artiq/gateware/targets/kc705_drtio_satellite.py
@@ -183,7 +183,7 @@ def __init__(self, cfg, medium, **kwargs):
         else:
             raise ValueError
         self.submodules.rx_synchronizer = gtx_7series.RXSynchronizer(
-            self.transceiver.rtio_clk_freq)
+            self.transceiver.rtio_clk_freq, initial_phase=180.0)
         self.submodules.drtio = DRTIOSatellite(
             self.transceiver, self.rx_synchronizer, rtio_channels)
         self.csr_devices.append("rx_synchronizer")

diff --git a/artiq/test/gateware/drtio/test_full_stack.py b/artiq/test/gateware/drtio/test_full_stack.py
@@ -174,15 +174,6 @@ def test_fifo_space():
             # check that some writes caused FIFO space requests
             self.assertGreater(max_wlen, 5)
 
-        def test_fifo_emptied():
-            # wait for all TTL events to execute
-            while len(ttl_changes) < len(correct_ttl_changes):
-                yield
-            # check "last timestamp passed" FIFO empty condition
-            delay(1000*8)
-            wlen = yield from write(0, 1)
-            self.assertEqual(wlen, 2)
-
         def test_tsc_error():
             err_present = yield from mgr.packet_err_present.read()
             self.assertEqual(err_present, 0)
@@ -203,6 +194,10 @@ def test_tsc_error():
             err_present = yield from mgr.packet_err_present.read()
             self.assertEqual(err_present, 0)
 
+        def wait_ttl_events():
+            while len(ttl_changes) < len(correct_ttl_changes):
+                yield
+
         def test():
             while not (yield from dut.master.link_layer.link_status.read()):
                 yield
@@ -213,8 +208,8 @@ def test():
             yield from test_sequence_error()
             yield from test_fifo_space()
             yield from test_large_data()
-            yield from test_fifo_emptied()
             yield from test_tsc_error()
+            yield from wait_ttl_events()
 
         @passive
         def check_ttls():