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base repository: m-labs/artiq
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  • 3 commits
  • 7 files changed
  • 1 contributor

Commits on Jan 4, 2017

  1. Unverified

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    c08fc8a View commit details
  2. update copyright year

    sbourdeauducq committed Jan 4, 2017
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    52fda27 View commit details
  3. ad9xxx -> ad9_dds

    sbourdeauducq committed Jan 4, 2017
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    86f6b39 View commit details
Showing with 27 additions and 29 deletions.
  1. +1 −1 README.rst
  2. +16 −12 artiq/firmware/runtime/moninj.rs
  3. +3 −3 artiq/gateware/{ad9xxx.py → ad9_dds.py}
  4. +5 −5 artiq/gateware/rtio/phy/dds.py
  5. +0 −6 artiq/gateware/targets/phaser.py
  6. +1 −1 doc/manual/conf.py
  7. +1 −1 doc/manual/introduction.rst
2 changes: 1 addition & 1 deletion README.rst
Original file line number Diff line number Diff line change
@@ -30,5 +30,5 @@ Website: https://m-labs.hk/artiq

`Cite ARTIQ <http://dx.doi.org/10.5281/zenodo.51303>`_ as ``Bourdeauducq, Sébastien et al. (2016). ARTIQ 1.0. Zenodo. 10.5281/zenodo.51303``.

Copyright (C) 2014-2016 M-Labs Limited.
Copyright (C) 2014-2017 M-Labs Limited.
Licensed under GNU GPL version 3 or any later version.
28 changes: 16 additions & 12 deletions artiq/firmware/runtime/moninj.rs
Original file line number Diff line number Diff line change
@@ -18,6 +18,7 @@ fn worker(socket: &mut UdpSocket) -> io::Result<()> {

match request {
Request::Monitor => {
#[cfg(has_dds)]
let mut dds_ftws = [0u32; (csr::CONFIG_RTIO_DDS_COUNT as usize *
csr::CONFIG_DDS_CHANNELS_PER_BUS as usize)];
let mut reply = Reply::default();
@@ -43,22 +44,25 @@ fn worker(socket: &mut UdpSocket) -> io::Result<()> {
}
}

reply.dds_rtio_first_channel = csr::CONFIG_RTIO_FIRST_DDS_CHANNEL as u16;
reply.dds_channels_per_bus = csr::CONFIG_DDS_CHANNELS_PER_BUS as u16;
#[cfg(has_dds)]
{
reply.dds_rtio_first_channel = csr::CONFIG_RTIO_FIRST_DDS_CHANNEL as u16;
reply.dds_channels_per_bus = csr::CONFIG_DDS_CHANNELS_PER_BUS as u16;

for j in 0..csr::CONFIG_RTIO_DDS_COUNT {
unsafe {
csr::rtio_moninj::mon_chan_sel_write(
(csr::CONFIG_RTIO_FIRST_DDS_CHANNEL + j) as u8);
for i in 0..csr::CONFIG_DDS_CHANNELS_PER_BUS {
csr::rtio_moninj::mon_probe_sel_write(i as u8);
csr::rtio_moninj::mon_value_update_write(1);
dds_ftws[(csr::CONFIG_DDS_CHANNELS_PER_BUS * j + i) as usize] =
csr::rtio_moninj::mon_value_read() as u32;
for j in 0..csr::CONFIG_RTIO_DDS_COUNT {
unsafe {
csr::rtio_moninj::mon_chan_sel_write(
(csr::CONFIG_RTIO_FIRST_DDS_CHANNEL + j) as u8);
for i in 0..csr::CONFIG_DDS_CHANNELS_PER_BUS {
csr::rtio_moninj::mon_probe_sel_write(i as u8);
csr::rtio_moninj::mon_value_update_write(1);
dds_ftws[(csr::CONFIG_DDS_CHANNELS_PER_BUS * j + i) as usize] =
csr::rtio_moninj::mon_value_read() as u32;
}
}
}
reply.dds_ftws = &dds_ftws;
}
reply.dds_ftws = &dds_ftws;

trace!("{} <- {:?}", addr, reply);
buf.clear();
6 changes: 3 additions & 3 deletions artiq/gateware/ad9xxx.py → artiq/gateware/ad9_dds.py
Original file line number Diff line number Diff line change
@@ -4,7 +4,7 @@
from misoc.interconnect import wishbone


class AD9xxx(Module):
class AD9_DDS(Module):
"""Wishbone interface to the AD9858 and AD9914 DDS chips.
Addresses 0-2**len(pads.a)-1 map the AD9xxx registers.
@@ -178,5 +178,5 @@ def __init__(self):

if __name__ == "__main__":
pads = _TestPads()
dut = AD9xxx(pads)
run_simulation(dut, _test_gen(dut.bus), vcd_name="ad9xxx.vcd")
dut = AD9_DDS(pads)
run_simulation(dut, _test_gen(dut.bus), vcd_name="ad9_dds.vcd")
10 changes: 5 additions & 5 deletions artiq/gateware/rtio/phy/dds.py
Original file line number Diff line number Diff line change
@@ -1,13 +1,13 @@
from migen import *

from artiq.gateware import ad9xxx
from artiq.gateware import ad9_dds
from artiq.gateware.rtio.phy.wishbone import RT2WB


class _AD9xxx(Module):
class _AD9_DDS(Module):
def __init__(self, ftw_base, pads, nchannels, onehot=False, **kwargs):
self.submodules._ll = ClockDomainsRenamer("rio_phy")(
ad9xxx.AD9xxx(pads, **kwargs))
ad9_dds.AD9_DDS(pads, **kwargs))
self.submodules._rt2wb = RT2WB(len(pads.a)+1, self._ll.bus)
self.rtlink = self._rt2wb.rtlink
self.probes = [Signal(32) for i in range(nchannels)]
@@ -56,6 +56,6 @@ def selected(c):
for c, (probe, ftw) in enumerate(zip(self.probes, ftws))])


class AD9914(_AD9xxx):
class AD9914(_AD9_DDS):
def __init__(self, *args, **kwargs):
_AD9xxx.__init__(self, 0x2d, *args, **kwargs)
_AD9_DDS.__init__(self, 0x2d, *args, **kwargs)
6 changes: 0 additions & 6 deletions artiq/gateware/targets/phaser.py
Original file line number Diff line number Diff line change
@@ -230,12 +230,6 @@ def __init__(self, cpu_type="or1k", **kwargs):
self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
rtio_channels.append(rtio.LogChannel())

# TODO: get rid of those bogus DDS defines
# currently moninj in the runtime requires them
self.config["RTIO_FIRST_DDS_CHANNEL"] = len(rtio_channels)
self.config["RTIO_DDS_COUNT"] = 1
self.config["DDS_CHANNELS_PER_BUS"] = 1

self.submodules.rtio_crg = _PhaserCRG(
platform, self.ad9154.jesd.cd_jesd.clk)
self.csr_devices.append("rtio_crg")
2 changes: 1 addition & 1 deletion doc/manual/conf.py
Original file line number Diff line number Diff line change
@@ -71,7 +71,7 @@ def __getattr__(cls, name):

# General information about the project.
project = 'ARTIQ'
copyright = '2014-2016, M-Labs Limited'
copyright = '2014-2017, M-Labs Limited'

# The version info for the project you're documenting, acts as replacement for
# |version| and |release|, also used in various other places throughout the
2 changes: 1 addition & 1 deletion doc/manual/introduction.rst
Original file line number Diff line number Diff line change
@@ -31,4 +31,4 @@ Website: https://m-labs.hk/artiq

`Cite ARTIQ <http://dx.doi.org/10.5281/zenodo.51303>`_ as ``Bourdeauducq, Sébastien et al. (2016). ARTIQ 1.0. Zenodo. 10.5281/zenodo.51303``.

Copyright (C) 2014-2016 M-Labs Limited. Licensed under GNU GPL version 3.
Copyright (C) 2014-2017 M-Labs Limited. Licensed under GNU GPL version 3.