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base repository: m-labs/artiq
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base: 2a7a8f91ca6f
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head repository: m-labs/artiq
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compare: 28a41a2f603a
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  • 2 commits
  • 5 files changed
  • 1 contributor

Commits on Jan 18, 2017

  1. Copy the full SHA
    5c0d402 View commit details
  2. gateware: fix aeb1ba8

    sbourdeauducq committed Jan 18, 2017
    Copy the full SHA
    28a41a2 View commit details
1 change: 0 additions & 1 deletion artiq/gateware/targets/kc705_dds.py
Original file line number Diff line number Diff line change
@@ -111,7 +111,6 @@ def __init__(self, cpu_type="or1k", **kwargs):
cpu_type=cpu_type,
sdram_controller_type="minicon",
l2_size=128*1024,
with_timer=False,
ident=artiq_version,
**kwargs)
AMPSoC.__init__(self)
1 change: 0 additions & 1 deletion artiq/gateware/targets/kc705_drtio_master.py
Original file line number Diff line number Diff line change
@@ -32,7 +32,6 @@ def __init__(self, cfg, medium, **kwargs):
cpu_type="or1k",
sdram_controller_type="minicon",
l2_size=128*1024,
with_timer=False,
ident=artiq_version,
**kwargs)
AMPSoC.__init__(self)
1 change: 0 additions & 1 deletion artiq/gateware/targets/phaser.py
Original file line number Diff line number Diff line change
@@ -168,7 +168,6 @@ def __init__(self, cpu_type="or1k", **kwargs):
cpu_type=cpu_type,
sdram_controller_type="minicon",
l2_size=128*1024,
with_timer=False,
ident=artiq_version,
**kwargs)
AMPSoC.__init__(self)
1 change: 0 additions & 1 deletion artiq/gateware/targets/pipistrello.py
Original file line number Diff line number Diff line change
@@ -158,7 +158,6 @@ def __init__(self, cpu_type="or1k", **kwargs):
BaseSoC.__init__(self,
cpu_type=cpu_type,
l2_size=64*1024,
with_timer=False,
ident=artiq_version,
clk_freq=75*1000*1000,
**kwargs)
6 changes: 4 additions & 2 deletions artiq/runtime/runtime.ld
Original file line number Diff line number Diff line change
@@ -21,12 +21,14 @@ SECTIONS
} > runtime

/* https://sourceware.org/bugzilla/show_bug.cgi?id=20475 */
.got : {
.got :
{
_GLOBAL_OFFSET_TABLE_ = .;
*(.got)
} > runtime

.got.plt : {
.got.plt :
{
*(.got.plt)
} > runtime