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base repository: m-labs/artiq
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head repository: m-labs/artiq
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compare: fe53bab953d2
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  • 2 commits
  • 17 files changed
  • 1 contributor

Commits on Jan 5, 2017

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    8be9a82 View commit details
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    fe53bab View commit details
2 changes: 1 addition & 1 deletion artiq/frontend/artiq_devtool.py
Original file line number Diff line number Diff line change
@@ -84,7 +84,7 @@ def drain(chan):
if action == "build":
logger.info("Building runtime")
try:
subprocess.check_call(["python3", "-m", "artiq.gateware.targets.kc705",
subprocess.check_call(["python3", "-m", "artiq.gateware.targets.kc705_dds",
"-H", "nist_clock",
"--no-compile-gateware",
"--output-dir", "/tmp/kc705"])
Original file line number Diff line number Diff line change
@@ -314,8 +314,8 @@ def __init__(self, cpu_type="or1k", **kwargs):

def main():
parser = argparse.ArgumentParser(
description="ARTIQ core device builder / KC705 "
"+ NIST Ions CLOCK/QC2 hardware adapters")
description="ARTIQ device binary builder / single-FPGA KC705-based "
"systems with AD9 DDS (NIST Ions hardware)")
builder_args(parser)
soc_kc705_args(parser)
parser.add_argument("-H", "--hw-adapter", default="nist_clock",
2 changes: 1 addition & 1 deletion artiq/gateware/targets/kc705_drtio_master.py
Original file line number Diff line number Diff line change
@@ -105,7 +105,7 @@ def __init__(self, cfg, medium, **kwargs):

def main():
parser = argparse.ArgumentParser(
description="ARTIQ with DRTIO on KC705 - Master")
description="ARTIQ device binary builder / KC705 DRTIO master")
builder_args(parser)
soc_kc705_args(parser)
parser.add_argument("-c", "--config", default="simple_gbe",
2 changes: 1 addition & 1 deletion artiq/gateware/targets/kc705_drtio_satellite.py
Original file line number Diff line number Diff line change
@@ -202,7 +202,7 @@ def __init__(self, cfg, medium, **kwargs):

def main():
parser = argparse.ArgumentParser(
description="ARTIQ with DRTIO on KC705 - Satellite")
description="ARTIQ device binary builder / KC705 DRTIO satellite")
builder_args(parser)
soc_kc705_args(parser)
parser.add_argument("-c", "--config", default="simple_gbe",
3 changes: 1 addition & 2 deletions artiq/gateware/targets/phaser.py
Original file line number Diff line number Diff line change
@@ -257,8 +257,7 @@ def __init__(self, cpu_type="or1k", **kwargs):

def main():
parser = argparse.ArgumentParser(
description="ARTIQ core device builder for "
"KC705+AD9154 hardware")
description="ARTIQ device binary builder / KC705 phaser demo")
builder_args(parser)
soc_kc705_args(parser)
args = parser.parse_args()
2 changes: 1 addition & 1 deletion artiq/gateware/targets/pipistrello.py
Original file line number Diff line number Diff line change
@@ -229,7 +229,7 @@ def __init__(self, cpu_type="or1k", **kwargs):

def main():
parser = argparse.ArgumentParser(
description="ARTIQ core device builder / Pipistrello demo")
description="ARTIQ device binary builder / Pipistrello demo")
builder_args(parser)
soc_pipistrello_args(parser)
args = parser.parse_args()
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2 changes: 1 addition & 1 deletion conda/artiq-kc705-nist_clock/build.sh
Original file line number Diff line number Diff line change
@@ -6,7 +6,7 @@ BUILD_SETTINGS_FILE=$HOME/.m-labs/build_settings.sh
SOC_PREFIX=$PREFIX/lib/python3.5/site-packages/artiq/binaries/kc705-nist_clock
mkdir -p $SOC_PREFIX

$PYTHON -m artiq.gateware.targets.kc705 -H nist_clock --toolchain vivado $MISOC_EXTRA_VIVADO_CMDLINE
$PYTHON -m artiq.gateware.targets.kc705_dds -H nist_clock --toolchain vivado $MISOC_EXTRA_VIVADO_CMDLINE
cp misoc_nist_clock_kc705/gateware/top.bit $SOC_PREFIX
cp misoc_nist_clock_kc705/software/bios/bios.bin $SOC_PREFIX
cp misoc_nist_clock_kc705/software/runtime/runtime.fbi $SOC_PREFIX
2 changes: 1 addition & 1 deletion conda/artiq-kc705-nist_qc2/build.sh
Original file line number Diff line number Diff line change
@@ -6,7 +6,7 @@ BUILD_SETTINGS_FILE=$HOME/.m-labs/build_settings.sh
SOC_PREFIX=$PREFIX/lib/python3.5/site-packages/artiq/binaries/kc705-nist_qc2
mkdir -p $SOC_PREFIX

$PYTHON -m artiq.gateware.targets.kc705 -H nist_qc2 --toolchain vivado $MISOC_EXTRA_VIVADO_CMDLINE
$PYTHON -m artiq.gateware.targets.kc705_dds -H nist_qc2 --toolchain vivado $MISOC_EXTRA_VIVADO_CMDLINE
cp misoc_nist_qc2_kc705/gateware/top.bit $SOC_PREFIX
cp misoc_nist_qc2_kc705/software/bios/bios.bin $SOC_PREFIX
cp misoc_nist_qc2_kc705/software/runtime/runtime.fbi $SOC_PREFIX
2 changes: 1 addition & 1 deletion doc/manual/installing_from_source.rst
Original file line number Diff line number Diff line change
@@ -170,7 +170,7 @@ These steps are required to generate gateware bitstream (``.bit``) files, build

* For KC705::

$ python3.5 -m artiq.gateware.targets.kc705 -H nist_clock # or nist_qc2
$ python3.5 -m artiq.gateware.targets.kc705_dds -H nist_clock # or nist_qc2

.. note:: Add ``--toolchain ise`` if you wish to use ISE instead of Vivado.