Skip to content
Permalink

Comparing changes

Choose two branches to see what’s changed or to start a new pull request. If you need to, you can also or learn more about diff comparisons.

Open a pull request

Create a new pull request by comparing changes across two branches. If you need to, you can also . Learn more about diff comparisons here.
base repository: m-labs/artiq
Failed to load repositories. Confirm that selected base ref is valid, then try again.
Loading
base: b29e2d5bfe19
Choose a base ref
...
head repository: m-labs/artiq
Failed to load repositories. Confirm that selected head ref is valid, then try again.
Loading
compare: de17908b38e6
Choose a head ref
  • 4 commits
  • 19 files changed
  • 1 contributor

Commits on Jan 24, 2017

  1. firmware: simplify ksupport build script.

    whitequark committed Jan 24, 2017
    Copy the full SHA
    209be73 View commit details
  2. firmware: rewrite cache flushing code in Rust.

    whitequark committed Jan 24, 2017
    Copy the full SHA
    2de3770 View commit details

Commits on Jan 25, 2017

  1. Copy the full SHA
    6414e40 View commit details
  2. Revert "Globally update UART baudrate to 921600."

    This reverts commit b29e2d5.
    
    This broke flterm firmware upload, which was the entire point
    of the whole exercise.
    whitequark committed Jan 25, 2017
    Copy the full SHA
    de17908 View commit details
1 change: 1 addition & 0 deletions artiq/firmware/Cargo.lock

Some generated files are not rendered by default. Learn more about how customized files appear on GitHub.

44 changes: 44 additions & 0 deletions artiq/firmware/libboard/cache.rs
Original file line number Diff line number Diff line change
@@ -0,0 +1,44 @@
use spr::{self, mfspr, mtspr};
use csr;
use mem;

pub fn flush_cpu_icache() {
unsafe {
let iccfgr = mfspr(spr::SPR_ICCFGR);
let ways = 1 << (iccfgr & spr::SPR_ICCFGR_NCW);
let set_size = 1 << ((iccfgr & spr::SPR_ICCFGR_NCS) >> 3);
let block_size = if iccfgr & spr::SPR_ICCFGR_CBS != 0 { 32 } else { 16 };
let size = set_size * ways * block_size;

let mut i = 0;
while i < size {
mtspr(spr::SPR_ICBIR, i);
i += block_size;
}
}
}

pub fn flush_cpu_dcache() {
unsafe {
let dccfgr = mfspr(spr::SPR_DCCFGR);
let ways = 1 << (dccfgr & spr::SPR_ICCFGR_NCW);
let set_size = 1 << ((dccfgr & spr::SPR_DCCFGR_NCS) >> 3);
let block_size = if dccfgr & spr::SPR_DCCFGR_CBS != 0 { 32 } else { 16 };
let size = set_size * ways * block_size;

let mut i = 0;
while i < size {
mtspr(spr::SPR_DCBIR, i);
i += block_size;
}
}
}

pub fn flush_l2_cache() {
unsafe {
for i in 0..2 * (csr::CONFIG_L2_SIZE as usize) / 4 {
let addr = mem::MAIN_RAM_BASE + i * 4;
asm!("l.lwz r0, 0($1)"::"r"(addr):"r0":"volatile")
}
}
}
6 changes: 1 addition & 5 deletions artiq/firmware/libboard/lib.rs
Original file line number Diff line number Diff line change
@@ -10,6 +10,7 @@ include!(concat!(env!("BUILDINC_DIRECTORY"), "/generated/mem.rs"));
include!(concat!(env!("BUILDINC_DIRECTORY"), "/generated/csr.rs"));
pub mod spr;
pub mod irq;
pub mod cache;
pub mod clock;
pub mod uart;
#[cfg(feature = "uart_console")]
@@ -34,11 +35,6 @@ pub mod ad9154;
#[cfg(feature = "uart_console")]
pub use uart_console::Console;

extern {
pub fn flush_cpu_dcache();
pub fn flush_l2_cache();
}

pub fn ident(buf: &mut [u8]) -> &str {
unsafe {
let len = ptr::read_volatile(csr::IDENTIFIER_MEM_BASE);
99 changes: 99 additions & 0 deletions artiq/firmware/libboard/spr.rs
Original file line number Diff line number Diff line change
@@ -57,6 +57,28 @@ pub const SPR_ESR_BASE: u32 = SPRGROUP_SYS + 64;
pub const SPR_ESR_LAST: u32 = SPRGROUP_SYS + 79;
pub const SPR_GPR_BASE: u32 = SPRGROUP_SYS + 1024;

/* Data MMU group */
pub const SPR_DMMUCR: u32 = SPRGROUP_DMMU + 0;
pub const SPR_DTLBEIR: u32 = SPRGROUP_DMMU + 2;

/* Instruction MMU group */
pub const SPR_IMMUCR: u32 = SPRGROUP_IMMU + 0;
pub const SPR_ITLBEIR: u32 = SPRGROUP_IMMU + 2;

/* Data cache group */
pub const SPR_DCCR: u32 = SPRGROUP_DC + 0;
pub const SPR_DCBPR: u32 = SPRGROUP_DC + 1;
pub const SPR_DCBFR: u32 = SPRGROUP_DC + 2;
pub const SPR_DCBIR: u32 = SPRGROUP_DC + 3;
pub const SPR_DCBWR: u32 = SPRGROUP_DC + 4;
pub const SPR_DCBLR: u32 = SPRGROUP_DC + 5;

/* Instruction cache group */
pub const SPR_ICCR: u32 = SPRGROUP_IC + 0;
pub const SPR_ICBPR: u32 = SPRGROUP_IC + 1;
pub const SPR_ICBIR: u32 = SPRGROUP_IC + 2;
pub const SPR_ICBLR: u32 = SPRGROUP_IC + 3;

// [snip]

/* PIC group */
@@ -89,3 +111,80 @@ pub const SPR_SR_FO: u32 = 0x00008000; /* Fixed one */
pub const SPR_SR_SUMRA: u32 = 0x00010000; /* Supervisor SPR read access */
pub const SPR_SR_RES: u32 = 0x0ffe0000; /* Reserved */
pub const SPR_SR_CID: u32 = 0xf0000000; /* Context ID */

/*
* Bit definitions for Data Cache Control register
*
*/
pub const SPR_DCCR_EW: u32 = 0x000000ff; /* Enable ways */

/*
* Bit definitions for Insn Cache Control register
*
*/
pub const SPR_ICCR_EW: u32 = 0x000000ff; /* Enable ways */

/*
* Bit definitions for Data Cache Configuration Register
*
*/
pub const SPR_DCCFGR_NCW: u32 = 0x00000007;
pub const SPR_DCCFGR_NCS: u32 = 0x00000078;
pub const SPR_DCCFGR_CBS: u32 = 0x00000080;
pub const SPR_DCCFGR_CWS: u32 = 0x00000100;
pub const SPR_DCCFGR_CCRI: u32 = 0x00000200;
pub const SPR_DCCFGR_CBIRI: u32 = 0x00000400;
pub const SPR_DCCFGR_CBPRI: u32 = 0x00000800;
pub const SPR_DCCFGR_CBLRI: u32 = 0x00001000;
pub const SPR_DCCFGR_CBFRI: u32 = 0x00002000;
pub const SPR_DCCFGR_CBWBRI: u32 = 0x00004000;

pub const SPR_DCCFGR_NCW_OFF: u32 = 0;
pub const SPR_DCCFGR_NCS_OFF: u32 = 3;
pub const SPR_DCCFGR_CBS_OFF: u32 = 7;

/*
* Bit definitions for Instruction Cache Configuration Register
*
*/
pub const SPR_ICCFGR_NCW: u32 = 0x00000007;
pub const SPR_ICCFGR_NCS: u32 = 0x00000078;
pub const SPR_ICCFGR_CBS: u32 = 0x00000080;
pub const SPR_ICCFGR_CCRI: u32 = 0x00000200;
pub const SPR_ICCFGR_CBIRI: u32 = 0x00000400;
pub const SPR_ICCFGR_CBPRI: u32 = 0x00000800;
pub const SPR_ICCFGR_CBLRI: u32 = 0x00001000;

pub const SPR_ICCFGR_NCW_OFF: u32 = 0;
pub const SPR_ICCFGR_NCS_OFF: u32 = 3;
pub const SPR_ICCFGR_CBS_OFF: u32 = 7;

/*
* Bit definitions for Data MMU Configuration Register
*
*/
pub const SPR_DMMUCFGR_NTW: u32 = 0x00000003;
pub const SPR_DMMUCFGR_NTS: u32 = 0x0000001C;
pub const SPR_DMMUCFGR_NAE: u32 = 0x000000E0;
pub const SPR_DMMUCFGR_CRI: u32 = 0x00000100;
pub const SPR_DMMUCFGR_PRI: u32 = 0x00000200;
pub const SPR_DMMUCFGR_TEIRI: u32 = 0x00000400;
pub const SPR_DMMUCFGR_HTR: u32 = 0x00000800;

pub const SPR_DMMUCFGR_NTW_OFF: u32 = 0;
pub const SPR_DMMUCFGR_NTS_OFF: u32 = 2;

/*
* Bit definitions for Instruction MMU Configuration Register
*
*/
pub const SPR_IMMUCFGR_NTW: u32 = 0x00000003;
pub const SPR_IMMUCFGR_NTS: u32 = 0x0000001C;
pub const SPR_IMMUCFGR_NAE: u32 = 0x000000E0;
pub const SPR_IMMUCFGR_CRI: u32 = 0x00000100;
pub const SPR_IMMUCFGR_PRI: u32 = 0x00000200;
pub const SPR_IMMUCFGR_TEIRI: u32 = 0x00000400;
pub const SPR_IMMUCFGR_HTR: u32 = 0x00000800;

pub const SPR_IMMUCFGR_NTW_OFF: u32 = 0;
pub const SPR_IMMUCFGR_NTS_OFF: u32 = 2;
3 changes: 3 additions & 0 deletions artiq/firmware/libksupport/Cargo.toml
Original file line number Diff line number Diff line change
@@ -9,6 +9,9 @@ name = "ksupport"
path = "lib.rs"
crate-type = ["staticlib"]

[build-dependencies]
build_artiq = { path = "../libbuild_artiq" }

[dependencies]
alloc_none = { path = "../liballoc_none" }
std_artiq = { path = "../libstd_artiq" }
15 changes: 2 additions & 13 deletions artiq/firmware/libksupport/build.rs
Original file line number Diff line number Diff line change
@@ -1,17 +1,6 @@
use std::env;
use std::path::Path;
use std::io::{BufRead, BufReader};
use std::fs::File;
extern crate build_artiq;

fn main() {
let out_dir = env::var("BUILDINC_DIRECTORY").unwrap();
let cfg_path = Path::new(&out_dir).join("generated").join("rust-cfg");
println!("cargo:rerun-if-changed={}", cfg_path.to_str().unwrap());

let f = BufReader::new(File::open(&cfg_path).unwrap());
for line in f.lines() {
println!("cargo:rustc-cfg={}", line.unwrap());
}

build_artiq::misoc_registers();
println!("cargo:rustc-cfg={}", "ksupport");
}
31 changes: 16 additions & 15 deletions artiq/firmware/runtime/analyzer.rs
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
use std::io::{self, Write};
use board::{self, csr};
use sched::{Io, TcpSocket};
use board::{csr, cache};
use sched::{Io, TcpListener, TcpStream};
use analyzer_proto::*;

const BUFFER_SIZE: usize = 512 * 1024;
@@ -35,12 +35,12 @@ fn disarm() {
unsafe {
csr::rtio_analyzer::enable_write(0);
while csr::rtio_analyzer::busy_read() != 0 {}
board::flush_cpu_dcache();
board::flush_l2_cache();
cache::flush_cpu_dcache();
cache::flush_l2_cache();
}
}

fn worker(socket: &mut TcpSocket) -> io::Result<()> {
fn worker(stream: &mut TcpStream) -> io::Result<()> {
let data = unsafe { &BUFFER.data[..] };
let overflow_occurred = unsafe { csr::rtio_analyzer::message_encoder_overflow_read() != 0 };
let total_byte_count = unsafe { csr::rtio_analyzer::dma_byte_count_read() };
@@ -56,12 +56,12 @@ fn worker(socket: &mut TcpSocket) -> io::Result<()> {
};
trace!("{:?}", header);

try!(header.write_to(socket));
try!(header.write_to(stream));
if wraparound {
try!(socket.write_all(&data[pointer..]));
try!(socket.write_all(&data[..pointer]));
try!(stream.write_all(&data[pointer..]));
try!(stream.write_all(&data[..pointer]));
} else {
try!(socket.write_all(&data[..pointer]));
try!(stream.write_all(&data[..pointer]));
}

Ok(())
@@ -71,20 +71,21 @@ pub fn thread(io: Io) {
// verify that the hack above works
assert!(::core::mem::align_of::<Buffer>() == 64);

let mut socket = TcpSocket::with_buffer_size(&io, 65535);
let listener = TcpListener::new(&io, 65535);
listener.listen(1382).expect("analyzer: cannot listen");

loop {
arm();

socket.listen(1382).expect("analyzer: cannot listen");
socket.accept().expect("analyzer: cannot accept");
info!("connection from {}", socket.remote_endpoint());
let mut stream = listener.accept().expect("analyzer: cannot accept");
info!("connection from {}", stream.remote_endpoint());

disarm();

match worker(&mut socket) {
match worker(&mut stream) {
Ok(()) => (),
Err(err) => error!("analyzer aborted: {}", err)
}
socket.close().expect("analyzer: cannot close");
stream.close().expect("analyzer: cannot close");
}
}
6 changes: 3 additions & 3 deletions artiq/firmware/runtime/mailbox.rs
Original file line number Diff line number Diff line change
@@ -1,7 +1,7 @@
use core::ptr::{read_volatile, write_volatile};
use board;
use board::{mem, cache};

const MAILBOX: *mut usize = board::mem::MAILBOX_BASE as *mut usize;
const MAILBOX: *mut usize = mem::MAILBOX_BASE as *mut usize;
static mut LAST: usize = 0;

pub unsafe fn send(data: usize) {
@@ -23,7 +23,7 @@ pub fn receive() -> usize {
0
} else {
if data != 0 {
board::flush_cpu_dcache()
cache::flush_cpu_dcache()
}
data
}
2 changes: 1 addition & 1 deletion artiq/firmware/runtime/moninj.rs
Original file line number Diff line number Diff line change
@@ -114,7 +114,7 @@ fn worker(socket: &mut UdpSocket) -> io::Result<()> {
}

pub fn thread(io: Io) {
let mut socket = UdpSocket::with_buffer_size(&io, 1, 512);
let mut socket = UdpSocket::new(&io, 1, 512);
socket.bind(3250);

loop {
8 changes: 4 additions & 4 deletions artiq/firmware/runtime/rpc_queue.rs
Original file line number Diff line number Diff line change
@@ -2,10 +2,10 @@

use core::ptr::{read_volatile, write_volatile};
use core::slice;
use board;
use board::{mem, cache};

const SEND_MAILBOX: *mut usize = (board::mem::MAILBOX_BASE + 4) as *mut usize;
const RECV_MAILBOX: *mut usize = (board::mem::MAILBOX_BASE + 8) as *mut usize;
const SEND_MAILBOX: *mut usize = (mem::MAILBOX_BASE + 4) as *mut usize;
const RECV_MAILBOX: *mut usize = (mem::MAILBOX_BASE + 8) as *mut usize;

const QUEUE_BEGIN: usize = 0x40400000;
const QUEUE_END: usize = 0x407fff80;
@@ -51,7 +51,7 @@ pub fn dequeue<T, E, F>(f: F) -> Result<T, E>
debug_assert!(!empty());

unsafe {
board::flush_cpu_dcache();
cache::flush_cpu_dcache();
let slice = slice::from_raw_parts_mut(read_volatile(RECV_MAILBOX) as *mut u8, QUEUE_CHUNK);
f(slice).and_then(|x| {
write_volatile(RECV_MAILBOX, next(read_volatile(RECV_MAILBOX)));
Loading