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base repository: m-labs/artiq
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head repository: m-labs/artiq
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  • 3 commits
  • 7 files changed
  • 1 contributor

Commits on Jan 18, 2017

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1 change: 1 addition & 0 deletions RELEASE_NOTES.rst
Original file line number Diff line number Diff line change
@@ -23,6 +23,7 @@ Release notes
* The DDS class names and setup options have changed, this requires an update of
the device database.
* ``int(a, width=b)`` has been removed. Use ``int32(a)`` and ``int64(a)``.
* The kc705 gateware target has been renamed kc705_dds.


2.1
3 changes: 1 addition & 2 deletions artiq/gateware/amp/__init__.py
Original file line number Diff line number Diff line change
@@ -1,2 +1 @@
from artiq.gateware.amp.kernel_cpu import KernelCPU
from artiq.gateware.amp.mailbox import Mailbox
from artiq.gateware.amp.soc import AMPSoC
17 changes: 6 additions & 11 deletions artiq/gateware/soc.py → artiq/gateware/amp/soc.py
Original file line number Diff line number Diff line change
@@ -5,30 +5,25 @@
from misoc.interconnect import wishbone
from misoc.integration.builder import *

from artiq.gateware import amp
from artiq.gateware.amp.kernel_cpu import KernelCPU
from artiq.gateware.amp.mailbox import Mailbox
from artiq import __artiq_dir__ as artiq_dir


class AMPSoC:
"""Contains timer, kernel CPU and mailbox for ARTIQ SoCs.
"""Contains kernel CPU and mailbox for ARTIQ SoCs.
Users must disable the timer from the platform SoC and provide
a "mailbox" entry in the memory map.
Users must provide a "mailbox" entry in the memory map.
"""
def __init__(self):
if not hasattr(self, "cpu"):
raise ValueError("Platform SoC must be initialized first")
if hasattr(self, "timer0"):
raise ValueError("Timer already exists. "
"Initialize platform SoC using with_timer=False")

self.submodules.timer0 = timer.Timer(width=64)

self.submodules.kernel_cpu = amp.KernelCPU(self.platform)
self.submodules.kernel_cpu = KernelCPU(self.platform)
self.add_cpulevel_sdram_if(self.kernel_cpu.wb_sdram)
self.csr_devices.append("kernel_cpu")

self.submodules.mailbox = amp.Mailbox(size=3)
self.submodules.mailbox = Mailbox(size=3)
self.add_wb_slave(mem_decoder(self.mem_map["mailbox"]),
self.mailbox.i1)
self.kernel_cpu.add_wb_slave(mem_decoder(self.mem_map["mailbox"]),
2 changes: 1 addition & 1 deletion artiq/gateware/targets/kc705_dds.py
Original file line number Diff line number Diff line change
@@ -14,7 +14,7 @@
from misoc.targets.kc705 import MiniSoC, soc_kc705_args, soc_kc705_argdict
from misoc.integration.builder import builder_args, builder_argdict

from artiq.gateware.soc import AMPSoC, build_artiq_soc
from artiq.gateware.amp import AMPSoC, build_artiq_soc
from artiq.gateware import rtio, nist_clock, nist_qc2
from artiq.gateware.rtio.phy import (ttl_simple, ttl_serdes_7series,
dds, spi)
2 changes: 1 addition & 1 deletion artiq/gateware/targets/kc705_drtio_master.py
Original file line number Diff line number Diff line change
@@ -10,7 +10,7 @@
from misoc.integration.builder import builder_args, builder_argdict

from artiq.gateware.ad9154_fmc_ebz import ad9154_fmc_ebz
from artiq.gateware.soc import AMPSoC, build_artiq_soc
from artiq.gateware.amp import AMPSoC, build_artiq_soc
from artiq.gateware import rtio
from artiq.gateware.rtio.phy import ttl_simple
from artiq.gateware.drtio.transceiver import gtx_7series
2 changes: 1 addition & 1 deletion artiq/gateware/targets/phaser.py
Original file line number Diff line number Diff line change
@@ -21,7 +21,7 @@
from misoc.targets.kc705 import MiniSoC, soc_kc705_args, soc_kc705_argdict
from misoc.integration.builder import builder_args, builder_argdict

from artiq.gateware.soc import AMPSoC, build_artiq_soc
from artiq.gateware.amp import AMPSoC, build_artiq_soc
from artiq.gateware import rtio
from artiq.gateware.ad9154_fmc_ebz import ad9154_fmc_ebz
from artiq.gateware.rtio.phy import (ttl_simple, ttl_serdes_7series,
2 changes: 1 addition & 1 deletion artiq/gateware/targets/pipistrello.py
Original file line number Diff line number Diff line change
@@ -17,7 +17,7 @@
soc_pipistrello_argdict)
from misoc.integration.builder import builder_args, builder_argdict

from artiq.gateware.soc import AMPSoC, build_artiq_soc
from artiq.gateware.amp import AMPSoC, build_artiq_soc
from artiq.gateware import rtio
from artiq.gateware.rtio.phy import ttl_simple, ttl_serdes_spartan6, dds, spi
from artiq import __version__ as artiq_version