rtio: do not reset DDS and SPI PHYs on RTIO reset (#503)

m-labs · Jul 11, 2016 · 078a9ab · 078a9ab
1 parent eceafad
commit 078a9ab
Showing 2 changed files with 2 additions and 2 deletions.
diff --git a/artiq/gateware/rtio/phy/dds.py b/artiq/gateware/rtio/phy/dds.py
@@ -6,7 +6,7 @@
 
 class _AD9xxx(Module):
     def __init__(self, ftw_base, pads, nchannels, onehot=False, **kwargs):
-        self.submodules._ll = ClockDomainsRenamer("rio")(
+        self.submodules._ll = ClockDomainsRenamer("rio_phy")(
             ad9xxx.AD9xxx(pads, **kwargs))
         self.submodules._rt2wb = RT2WB(len(pads.a)+1, self._ll.bus)
         self.rtlink = self._rt2wb.rtlink

diff --git a/artiq/gateware/rtio/phy/spi.py b/artiq/gateware/rtio/phy/spi.py
@@ -6,7 +6,7 @@
 
 class SPIMaster(Module):
     def __init__(self, pads, **kwargs):
-        self.submodules._ll = ClockDomainsRenamer("rio")(
+        self.submodules._ll = ClockDomainsRenamer("rio_phy")(
             SPIMasterWB(pads, **kwargs))
         self.submodules._rt2wb = RT2WB(2, self._ll.bus)
         self.rtlink = self._rt2wb.rtlink