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target/pipistrello: shrink TTL FIFOs
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sbourdeauducq committed Jul 14, 2016
1 parent fe2b249 commit ce73e8e
Showing 1 changed file with 2 additions and 2 deletions.
4 changes: 2 additions & 2 deletions artiq/gateware/targets/pipistrello.py
Original file line number Diff line number Diff line change
@@ -177,7 +177,7 @@ def __init__(self, cpu_type="or1k", **kwargs):
phy = ttl_serdes_spartan6.Inout_4X(platform.request("pmt", i),
self.rtio_crg.rtiox4_stb)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512,
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=64,
ofifo_depth=4))

# the last TTL is used for ClockGen
@@ -192,7 +192,7 @@ def __init__(self, cpu_type="or1k", **kwargs):
phy = ttl_simple.Output(platform.request("ttl", i))

self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ofifo_depth=256))
rtio_channels.append(rtio.Channel.from_phy(phy, ofifo_depth=64))

phy = ttl_simple.Output(platform.request("ext_led", 0))
self.submodules += phy

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