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base repository: azonenberg/openfpga
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  • 6 commits
  • 6 files changed
  • 1 contributor

Commits on Jun 11, 2017

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Showing with 3,957 additions and 17 deletions.
  1. +153 −2 src/xc2bit/src/bitstream.rs
  2. +12 −4 src/xc2bit/src/fb.rs
  3. +42 −6 src/xc2bit/src/fusemap_logical.rs
  4. +286 −2 src/xc2bit/src/iob.rs
  5. +1 −1 src/xc2bit/src/lib.rs
  6. +3,463 −2 src/xc2bit/src/zia.rs
155 changes: 153 additions & 2 deletions src/xc2bit/src/bitstream.rs
Original file line number Diff line number Diff line change
@@ -185,7 +185,22 @@ impl XC2Bitstream {
}
})
},
_ => Err("invalid device")
XC2Device::XC2C512 => {
Ok(XC2Bitstream {
speed_grade: speed_grade,
package: package,
bits: XC2BitstreamBits::XC2C512 {
fb: [XC2BitstreamFB::default(); 32],
iobs: [XC2MCLargeIOB::default(); 270],
global_nets: XC2GlobalNets::default(),
ivoltage: [false, false, false, false],
ovoltage: [false, false, false, false],
data_gate: false,
use_vref: false,
clock_div: XC2ClockDiv::default(),
}
})
}
}
}
}
@@ -396,6 +411,23 @@ fn read_384_clock_div_logical(fuses: &[bool]) -> XC2ClockDiv {
}
}

/// Internal function to read the clock divider configuration from a 512-macrocell part
fn read_512_clock_div_logical(fuses: &[bool]) -> XC2ClockDiv {
XC2ClockDiv {
delay: !fuses[296381],
enabled: !fuses[296377],
div_ratio: match (fuses[296378], fuses[296379], fuses[296380]) {
(false, false, false) => XC2ClockDivRatio::Div2,
(false, false, true) => XC2ClockDivRatio::Div4,
(false, true, false) => XC2ClockDivRatio::Div6,
(false, true, true) => XC2ClockDivRatio::Div8,
( true, false, false) => XC2ClockDivRatio::Div10,
( true, false, true) => XC2ClockDivRatio::Div12,
( true, true, false) => XC2ClockDivRatio::Div14,
( true, true, true) => XC2ClockDivRatio::Div16,
}
}
}

/// The actual bitstream bits for each possible Coolrunner-II part
pub enum XC2BitstreamBits {
@@ -522,6 +554,24 @@ pub enum XC2BitstreamBits {
///
/// `false` = low, `true` = high
ovoltage: [bool; 4],
},
XC2C512 {
fb: [XC2BitstreamFB; 32],
iobs: [XC2MCLargeIOB; 270],
global_nets: XC2GlobalNets,
clock_div: XC2ClockDiv,
/// Whether the DataGate feature is used
data_gate: bool,
/// Whether I/O standards with VREF are used
use_vref: bool,
/// Voltage level control for each I/O bank
///
/// `false` = low, `true` = high
ivoltage: [bool; 4],
/// Voltage level control for each I/O bank
///
/// `false` = low, `true` = high
ovoltage: [bool; 4],
}
}

@@ -536,6 +586,7 @@ impl XC2BitstreamBits {
&XC2BitstreamBits::XC2C128{..} => XC2Device::XC2C128,
&XC2BitstreamBits::XC2C256{..} => XC2Device::XC2C256,
&XC2BitstreamBits::XC2C384{..} => XC2Device::XC2C384,
&XC2BitstreamBits::XC2C512{..} => XC2Device::XC2C512,
}
}

@@ -549,6 +600,7 @@ impl XC2BitstreamBits {
&XC2BitstreamBits::XC2C128{ref fb, ..} => fb,
&XC2BitstreamBits::XC2C256{ref fb, ..} => fb,
&XC2BitstreamBits::XC2C384{ref fb, ..} => fb,
&XC2BitstreamBits::XC2C512{ref fb, ..} => fb,
}
}

@@ -562,6 +614,7 @@ impl XC2BitstreamBits {
&XC2BitstreamBits::XC2C128{ref global_nets, ..} => global_nets,
&XC2BitstreamBits::XC2C256{ref global_nets, ..} => global_nets,
&XC2BitstreamBits::XC2C384{ref global_nets, ..} => global_nets,
&XC2BitstreamBits::XC2C512{ref global_nets, ..} => global_nets,
}
}

@@ -648,6 +701,23 @@ impl XC2BitstreamBits {
write!(writer, "VREF used: {}\n", if *use_vref {"high"} else {"low"})?;
clock_div.dump_human_readable(writer)?;
global_nets.dump_human_readable(writer)?;
},
&XC2BitstreamBits::XC2C512 {ref global_nets, ref ivoltage, ref ovoltage, ref clock_div, ref data_gate,
ref use_vref, ..} => {

write!(writer, "device type: XC2C512\n")?;
write!(writer, "bank 0 output voltage range: {}\n", if ovoltage[0] {"high"} else {"low"})?;
write!(writer, "bank 1 output voltage range: {}\n", if ovoltage[1] {"high"} else {"low"})?;
write!(writer, "bank 2 output voltage range: {}\n", if ovoltage[2] {"high"} else {"low"})?;
write!(writer, "bank 3 output voltage range: {}\n", if ovoltage[3] {"high"} else {"low"})?;
write!(writer, "bank 0 input voltage range: {}\n", if ivoltage[0] {"high"} else {"low"})?;
write!(writer, "bank 1 input voltage range: {}\n", if ivoltage[1] {"high"} else {"low"})?;
write!(writer, "bank 2 input voltage range: {}\n", if ivoltage[2] {"high"} else {"low"})?;
write!(writer, "bank 3 input voltage range: {}\n", if ivoltage[3] {"high"} else {"low"})?;
write!(writer, "DataGate used: {}\n", if *data_gate {"high"} else {"low"})?;
write!(writer, "VREF used: {}\n", if *use_vref {"high"} else {"low"})?;
clock_div.dump_human_readable(writer)?;
global_nets.dump_human_readable(writer)?;
}
}

@@ -682,6 +752,11 @@ impl XC2BitstreamBits {
iobs[i].dump_human_readable(self.device_type(), i as u32, writer)?;
}
},
&XC2BitstreamBits::XC2C512 {ref iobs, ..} => {
for i in 0..self.device_type().num_iobs() {
iobs[i].dump_human_readable(self.device_type(), i as u32, writer)?;
}
},
}

// Input-only pin
@@ -761,6 +836,17 @@ impl XC2BitstreamBits {
write_large_mc_to_jed(writer, XC2Device::XC2C384, &fb[fb_i], iobs, fb_i, fuse_base)?;
}
}
&XC2BitstreamBits::XC2C512 {ref fb, ref iobs, ..} => {
// Each FB
for fb_i in 0..32 {
let fuse_base = fb_fuse_idx(XC2Device::XC2C512, fb_i as u32);

fb[fb_i].write_to_jed(XC2Device::XC2C512, fuse_base, writer)?;

// Macrocells
write_large_mc_to_jed(writer, XC2Device::XC2C512, &fb[fb_i], iobs, fb_i, fuse_base)?;
}
}
}

// GCK
@@ -817,6 +903,21 @@ impl XC2BitstreamBits {
})?;
write!(writer, "L209335 {}*\n", if clock_div.delay {"0"} else {"1"})?;
},
&XC2BitstreamBits::XC2C512 {clock_div, ..} => {
write!(writer, "L296377 {}{}*\n",
if clock_div.enabled {"0"} else {"1"},
match clock_div.div_ratio {
XC2ClockDivRatio::Div2 => "000",
XC2ClockDivRatio::Div4 => "001",
XC2ClockDivRatio::Div6 => "010",
XC2ClockDivRatio::Div8 => "011",
XC2ClockDivRatio::Div10 => "100",
XC2ClockDivRatio::Div12 => "101",
XC2ClockDivRatio::Div14 => "110",
XC2ClockDivRatio::Div16 => "111",
})?;
write!(writer, "L296381 {}*\n", if clock_div.delay {"0"} else {"1"})?;
},
_ => {},
}

@@ -889,6 +990,18 @@ impl XC2BitstreamBits {

write!(writer, "L209356 {}*\n", if *use_vref {"0"} else {"1"})?;
}
&XC2BitstreamBits::XC2C512 {ref ivoltage, ref ovoltage, ref data_gate, ref use_vref, ..} => {
write!(writer, "L296393 {}*\n", if *data_gate {"0"} else {"1"})?;

write!(writer, "L296394 {}{}{}{}*\n",
if ivoltage[0] {"0"} else {"1"}, if ivoltage[1] {"0"} else {"1"},
if ivoltage[2] {"0"} else {"1"}, if ivoltage[3] {"0"} else {"1"})?;
write!(writer, "L296398 {}{}{}{}*\n",
if ovoltage[0] {"0"} else {"1"}, if ovoltage[1] {"0"} else {"1"},
if ovoltage[2] {"0"} else {"1"}, if ovoltage[3] {"0"} else {"1"})?;

write!(writer, "L296402 {}*\n", if *use_vref {"0"} else {"1"})?;
}
}

// A-variant bank voltages
@@ -1146,6 +1259,37 @@ pub fn read_384_bitstream_logical(fuses: &[bool]) -> Result<XC2BitstreamBits, &'
})
}

/// Internal function for parsing an XC2C512 bitstream
pub fn read_512_bitstream_logical(fuses: &[bool]) -> Result<XC2BitstreamBits, &'static str> {
let mut fb = [XC2BitstreamFB::default(); 32];
let mut iobs = [XC2MCLargeIOB::default(); 270];

read_bitstream_logical_common_large(fuses, XC2Device::XC2C512, &mut fb, &mut iobs)?;

let global_nets = read_global_nets_logical(XC2Device::XC2C512, fuses);

Ok(XC2BitstreamBits::XC2C512 {
fb: fb,
iobs: iobs,
global_nets: global_nets,
clock_div: read_512_clock_div_logical(fuses),
data_gate: !fuses[296393],
use_vref: !fuses[296402],
ivoltage: [
!fuses[296394],
!fuses[296395],
!fuses[296396],
!fuses[296397],
],
ovoltage: [
!fuses[296398],
!fuses[296399],
!fuses[296400],
!fuses[296401],
]
})
}

/// Processes a fuse array into a bitstream object
pub fn process_jed(fuses: &[bool], device: &str) -> Result<XC2Bitstream, &'static str> {
let device_combination = parse_part_name_string(device);
@@ -1216,6 +1360,13 @@ pub fn process_jed(fuses: &[bool], device: &str) -> Result<XC2Bitstream, &'stati
bits: bits,
})
},
_ => Err("unsupported part"),
XC2Device::XC2C512 => {
let bits = read_512_bitstream_logical(fuses)?;
Ok(XC2Bitstream {
speed_grade: spd,
package: pkg,
bits: bits,
})
},
}
}
16 changes: 12 additions & 4 deletions src/xc2bit/src/fb.rs
Original file line number Diff line number Diff line change
@@ -32,8 +32,9 @@ use *;
use pla::{read_and_term_logical, read_or_term_logical};
use mc::{read_small_ff_logical, read_large_ff_logical, read_large_buried_ff_logical};
use zia::{encode_32_zia_choice, encode_64_zia_choice, encode_128_zia_choice, encode_256_zia_choice,
encode_384_zia_choice, read_32_zia_fb_row_logical, read_64_zia_fb_row_logical, read_128_zia_fb_row_logical,
read_256_zia_fb_row_logical, read_384_zia_fb_row_logical, zia_get_row_width};
encode_384_zia_choice, encode_512_zia_choice, read_32_zia_fb_row_logical, read_64_zia_fb_row_logical,
read_128_zia_fb_row_logical, read_256_zia_fb_row_logical, read_384_zia_fb_row_logical,
read_512_zia_fb_row_logical, zia_get_row_width};

/// Represents a collection of all the parts that make up one function block
#[derive(Copy)]
@@ -183,7 +184,14 @@ impl XC2BitstreamFB {
write!(writer, "{}", if zia_choice_bits[j] {"1"} else {"0"})?;
}
},
_ => unreachable!(),
XC2Device::XC2C512 => {
let zia_choice_bits = encode_512_zia_choice(i as u32, self.zia_bits[i].selected)
// FIXME: Fold this into the error system??
.expect("invalid ZIA input");
for j in 0..zia_choice_bits.len() {
write!(writer, "{}", if zia_choice_bits[j] {"1"} else {"0"})?;
}
},
}
write!(writer, "*\n")?;
}
@@ -249,7 +257,7 @@ pub fn read_fb_logical(device: XC2Device, fuses: &[bool], fb: u32, fuse_base: us
XC2Device::XC2C128 => read_128_zia_fb_row_logical,
XC2Device::XC2C256 => read_256_zia_fb_row_logical,
XC2Device::XC2C384 => read_384_zia_fb_row_logical,
_ => unreachable!(),
XC2Device::XC2C512 => read_512_zia_fb_row_logical,
};

let mut and_terms = [XC2PLAAndTerm::default(); ANDTERMS_PER_FB];
48 changes: 42 additions & 6 deletions src/xc2bit/src/fusemap_logical.rs
Original file line number Diff line number Diff line change
@@ -107,8 +107,44 @@ pub fn fb_fuse_idx(device: XC2Device, fb: u32) -> usize {
23 => 200606,
_ => unreachable!(),
}
},
XC2Device::XC2C512 => {
match fb {
0 => 0,
1 => 9256,
2 => 18512,
3 => 27781,
4 => 37037,
5 => 46306,
6 => 55562,
7 => 64831,
8 => 74087,
9 => 83343,
10 => 92599,
11 => 101855,
12 => 111124,
13 => 120380,
14 => 129649,
15 => 138905,
16 => 148174,
17 => 157443,
18 => 166699,
19 => 175968,
20 => 185224,
21 => 194493,
22 => 203749,
23 => 213018,
24 => 222274,
25 => 231530,
26 => 240799,
27 => 250055,
28 => 259324,
29 => 268580,
30 => 277849,
31 => 287105,
_ => unreachable!(),
}
}
_ => unreachable!(),
}
}

@@ -119,7 +155,7 @@ pub fn gck_fuse_idx(device: XC2Device) -> usize {
XC2Device::XC2C128 => 55316,
XC2Device::XC2C256 => 123224,
XC2Device::XC2C384 => 209328,
_ => unreachable!(),
XC2Device::XC2C512 => 296374,
}
}

@@ -130,7 +166,7 @@ pub fn gsr_fuse_idx(device: XC2Device) -> usize {
XC2Device::XC2C128 => 55324,
XC2Device::XC2C256 => 123232,
XC2Device::XC2C384 => 209336,
_ => unreachable!(),
XC2Device::XC2C512 => 296382,
}
}

@@ -141,7 +177,7 @@ pub fn gts_fuse_idx(device: XC2Device) -> usize {
XC2Device::XC2C128 => 55326,
XC2Device::XC2C256 => 123234,
XC2Device::XC2C384 => 209338,
_ => unreachable!(),
XC2Device::XC2C512 => 296384,
}
}

@@ -152,7 +188,7 @@ pub fn global_term_fuse_idx(device: XC2Device) -> usize {
XC2Device::XC2C128 => 55334,
XC2Device::XC2C256 => 123242,
XC2Device::XC2C384 => 209346,
_ => unreachable!(),
XC2Device::XC2C512 => 296392,
}
}

@@ -165,6 +201,6 @@ pub fn total_logical_fuse_count(device: XC2Device) -> usize {
XC2Device::XC2C128 => 55341,
XC2Device::XC2C256 => 123249,
XC2Device::XC2C384 => 209357,
_ => unreachable!(),
XC2Device::XC2C512 => 296403,
}
}
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