Skip to content
Permalink

Comparing changes

Choose two branches to see what’s changed or to start a new pull request. If you need to, you can also or learn more about diff comparisons.

Open a pull request

Create a new pull request by comparing changes across two branches. If you need to, you can also . Learn more about diff comparisons here.
base repository: azonenberg/yosys
Failed to load repositories. Confirm that selected base ref is valid, then try again.
Loading
base: 05df3dbee434
Choose a base ref
...
head repository: azonenberg/yosys
Failed to load repositories. Confirm that selected head ref is valid, then try again.
Loading
compare: 129984e115d3
Choose a head ref
  • 4 commits
  • 5 files changed
  • 1 contributor

Commits on May 30, 2017

  1. Copy the full SHA
    c365e33 View commit details

Commits on May 31, 2017

  1. Copy the full SHA
    e7a984a View commit details
  2. Copy the full SHA
    0290b68 View commit details

Commits on Jun 1, 2017

  1. Copy the full SHA
    129984e View commit details
Showing with 44 additions and 9 deletions.
  1. +1 −1 Makefile
  2. +20 −8 backends/aiger/aiger.cc
  3. +8 −0 frontends/verilog/verilog_parser.y
  4. +1 −0 techlibs/common/Makefile.inc
  5. +14 −0 techlibs/common/dff2ff.v
2 changes: 1 addition & 1 deletion Makefile
Original file line number Diff line number Diff line change
@@ -94,7 +94,7 @@ OBJS = kernel/version_$(GIT_REV).o
# is just a symlink to your actual ABC working directory, as 'make mrproper'
# will remove the 'abc' directory and you do not want to accidentally
# delete your work on ABC..
ABCREV = e79576e10d72
ABCREV = efbf7f13ea9e
ABCPULL = 1
ABCURL ?= https://bitbucket.org/alanmi/abc
ABCMKARGS = CC="$(CXX)" CXX="$(CXX)"
28 changes: 20 additions & 8 deletions backends/aiger/aiger.cc
Original file line number Diff line number Diff line change
@@ -484,6 +484,8 @@ struct AigerWriter

if (symbols_mode)
{
dict<string, vector<string>> symbols;

for (auto wire : module->wires())
{
if (wire->name[0] == '$')
@@ -500,38 +502,48 @@ struct AigerWriter
int a = aig_map.at(sig[i]);
log_assert((a & 1) == 0);
if (GetSize(wire) != 1)
f << stringf("i%d %s[%d]\n", (a >> 1)-1, log_id(wire), i);
symbols[stringf("i%d", (a >> 1)-1)].push_back(stringf("%s[%d]", log_id(wire), i));
else
f << stringf("i%d %s\n", (a >> 1)-1, log_id(wire));
symbols[stringf("i%d", (a >> 1)-1)].push_back(stringf("%s", log_id(wire)));
}

if (wire->port_output) {
int o = ordered_outputs.at(sig[i]);
if (GetSize(wire) != 1)
f << stringf("%c%d %s[%d]\n", miter_mode ? 'b' : 'o', o, log_id(wire), i);
symbols[stringf("%c%d", miter_mode ? 'b' : 'o', o)].push_back(stringf("%s[%d]", log_id(wire), i));
else
f << stringf("%c%d %s\n", miter_mode ? 'b' : 'o', o, log_id(wire));
symbols[stringf("%c%d", miter_mode ? 'b' : 'o', o)].push_back(stringf("%s", log_id(wire)));
}

if (init_inputs.count(sig[i])) {
int a = init_inputs.at(sig[i]);
log_assert((a & 1) == 0);
if (GetSize(wire) != 1)
f << stringf("i%d init:%s[%d]\n", (a >> 1)-1, log_id(wire), i);
symbols[stringf("i%d", (a >> 1)-1)].push_back(stringf("init:%s[%d]", log_id(wire), i));
else
f << stringf("i%d init:%s\n", (a >> 1)-1, log_id(wire));
symbols[stringf("i%d", (a >> 1)-1)].push_back(stringf("init:%s", log_id(wire)));
}

if (ordered_latches.count(sig[i])) {
int l = ordered_latches.at(sig[i]);
const char *p = (zinit_mode && (aig_latchinit.at(l) == 1)) ? "!" : "";
if (GetSize(wire) != 1)
f << stringf("l%d %s%s[%d]\n", l, p, log_id(wire), i);
symbols[stringf("l%d", l)].push_back(stringf("%s%s[%d]", p, log_id(wire), i));
else
f << stringf("l%d %s%s\n", l, p, log_id(wire));
symbols[stringf("l%d", l)].push_back(stringf("%s%s", p, log_id(wire)));
}
}
}

symbols.sort();

for (auto &sym : symbols) {
f << sym.first;
std::sort(sym.second.begin(), sym.second.end());
for (auto &s : sym.second)
f << " " << s;
f << std::endl;
}
}

f << stringf("c\nGenerated by %s\n", yosys_version_str);
8 changes: 8 additions & 0 deletions frontends/verilog/verilog_parser.y
Original file line number Diff line number Diff line change
@@ -1537,10 +1537,18 @@ basic_expr:
$$ = new AstNode(AST_BIT_AND, $1, $4);
append_attr($$, $3);
} |
basic_expr OP_NAND attr basic_expr {
$$ = new AstNode(AST_BIT_NOT, new AstNode(AST_BIT_AND, $1, $4));
append_attr($$, $3);
} |
basic_expr '|' attr basic_expr {
$$ = new AstNode(AST_BIT_OR, $1, $4);
append_attr($$, $3);
} |
basic_expr OP_NOR attr basic_expr {
$$ = new AstNode(AST_BIT_NOT, new AstNode(AST_BIT_OR, $1, $4));
append_attr($$, $3);
} |
basic_expr '^' attr basic_expr {
$$ = new AstNode(AST_BIT_XOR, $1, $4);
append_attr($$, $3);
1 change: 1 addition & 0 deletions techlibs/common/Makefile.inc
Original file line number Diff line number Diff line change
@@ -24,5 +24,6 @@ $(eval $(call add_share_file,share,techlibs/common/simcells.v))
$(eval $(call add_share_file,share,techlibs/common/techmap.v))
$(eval $(call add_share_file,share,techlibs/common/pmux2mux.v))
$(eval $(call add_share_file,share,techlibs/common/adff2dff.v))
$(eval $(call add_share_file,share,techlibs/common/dff2ff.v))
$(eval $(call add_share_file,share,techlibs/common/cells.lib))

14 changes: 14 additions & 0 deletions techlibs/common/dff2ff.v
Original file line number Diff line number Diff line change
@@ -0,0 +1,14 @@
(* techmap_celltype = "$dff" *)
module dff2ff (CLK, D, Q);
parameter WIDTH = 1;
parameter CLK_POLARITY = 1;

input CLK;
input [WIDTH-1:0] D;
output reg [WIDTH-1:0] Q;

wire [1023:0] _TECHMAP_DO_ = "proc;;";

always @($global_clock)
Q <= D;
endmodule