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base repository: azonenberg/yosys
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compare: dca3b3cd5f81
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  • 3 commits
  • 5 files changed
  • 1 contributor

Commits on May 17, 2017

  1. Add workaround for CBMC bug to SimpleC back-end

    @cliffordwolf
    cliffordwolf committed May 17, 2017
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    2122ae6 View commit details

Commits on May 23, 2017

  1. Merge branch 'master' of github.com:cliffordwolf/yosys

    @cliffordwolf
    cliffordwolf committed May 23, 2017
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    664ba4d View commit details

  2. Add examples/osu035

    @cliffordwolf
    cliffordwolf committed May 23, 2017
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    dca3b3c View commit details
Showing with 33 additions and 1 deletion.
  1. +3 −1 backends/simplec/simplec.cc
  2. +3 −0 examples/osu035/.gitignore
  3. +13 −0 examples/osu035/Makefile
  4. +3 −0 examples/osu035/example.v
  5. +11 −0 examples/osu035/example.ys
4 changes: 3 additions & 1 deletion backends/simplec/simplec.cc
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Original file line number Diff line number Diff line change
@@ -482,7 +482,9 @@ struct SimplecWorker
string a_expr = a.wire ? util_get_bit(work->prefix + cid(a.wire->name), a.wire->width, a.offset) : a.data ? "1" : "0";
string b_expr = b.wire ? util_get_bit(work->prefix + cid(b.wire->name), b.wire->width, b.offset) : b.data ? "1" : "0";
string s_expr = s.wire ? util_get_bit(work->prefix + cid(s.wire->name), s.wire->width, s.offset) : s.data ? "1" : "0";
string expr = stringf("%s ? %s : %s", s_expr.c_str(), b_expr.c_str(), a_expr.c_str());

// casts to bool are a workaround for CBMC bug (https://github.com/diffblue/cbmc/issues/933)
string expr = stringf("%s ? (bool)%s : (bool)%s", s_expr.c_str(), b_expr.c_str(), a_expr.c_str());

log_assert(y.wire);
funct_declarations.push_back(util_set_bit(work->prefix + cid(y.wire->name), y.wire->width, y.offset, expr) +
3 changes: 3 additions & 0 deletions examples/osu035/.gitignore
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@@ -0,0 +1,3 @@
osu035_stdcells.lib
example.yslog
example.edif
13 changes: 13 additions & 0 deletions examples/osu035/Makefile
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@@ -0,0 +1,13 @@

example.edif: example.ys example.v osu035_stdcells.lib
yosys -l example.yslog -q example.ys

osu035_stdcells.lib:
rm -f osu035_stdcells.lib.part osu035_stdcells.lib
wget -O osu035_stdcells.lib.part https://vlsiarch.ecen.okstate.edu/flows/MOSIS_SCMOS/latest/cadence/lib/ami035/signalstorm/osu035_stdcells.lib
mv osu035_stdcells.lib.part osu035_stdcells.lib

clean:
rm -f osu035_stdcells.lib
rm -f example.yslog example.edif

3 changes: 3 additions & 0 deletions examples/osu035/example.v
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@@ -0,0 +1,3 @@
module top (input clk, input [7:0] a, b, output reg [15:0] c);
always @(posedge clk) c <= a * b;
endmodule
11 changes: 11 additions & 0 deletions examples/osu035/example.ys
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@@ -0,0 +1,11 @@
read_verilog example.v
read_liberty -lib osu035_stdcells.lib

synth -top top

dfflibmap -liberty osu035_stdcells.lib
abc -liberty osu035_stdcells.lib
opt_clean

stat -liberty osu035_stdcells.lib
write_edif example.edif