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azonenbergazonenberg
committedJun 15, 2017
XC2CZIA: added initial ZIA structure for 32-macrocell device
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Diff for: ‎hdl/xc2c-model/XC2CZIA.v

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`default_nettype none
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/***********************************************************************************************************************
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* Copyright (C) 2016-2017 Andrew Zonenberg and contributors *
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* *
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* This program is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser General *
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* Public License as published by the Free Software Foundation; either version 2.1 of the License, or (at your option) *
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* any later version. *
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* *
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* This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied *
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* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for *
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* more details. *
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* *
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* You should have received a copy of the GNU Lesser General Public License along with this program; if not, you may *
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* find one here: *
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* https://www.gnu.org/licenses/old-licenses/lgpl-2.1.txt *
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* or you may search the http://www.gnu.org website for the version 2.1 license, or you may write to the Free Software *
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA *
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**********************************************************************************************************************/
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/**
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@brief Global routing fabric - the "Zero Power Interconnect Array"
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*/
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module XC2CZIA(
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dedicated_in, ibuf_in, macrocell_in,
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zia_out,
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config_bits);
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////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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// Device configuration
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parameter MACROCELLS = 32; //A variant implied for 32/64, no support for base version
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initial begin
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if(MACROCELLS != 32) begin
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$display("ZIA not implemented for other device densities");
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$finish;
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end
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end
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localparam NUM_IBUFS = 32; //TODO: function or something
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localparam NUM_MCELLS = 32;
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localparam BITS_PER_ROW = 8;
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////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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// Inputs
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input wire dedicated_in; //only present in 32a
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input wire[NUM_IBUFS-1:0] ibuf_in; //Inputs (from flipflop or input buffer)
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//{fb2, fb1}
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input wire[NUM_MCELLS-1:0] macrocell_in; //Inputs (from XOR gate or flipflop)
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//{fb2, fb1}
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output reg[39:0] zia_out; //40 outputs to the function block
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input wire[40 * BITS_PER_ROW-1 : 0] config_bits; //The actual config bitstream for this ZIA block
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////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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// Reshuffle the bitstream into proper rows
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reg[BITS_PER_ROW-1:0] row_config[39:0];
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integer i;
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always @(*) begin
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for(i=0; i<40; i=i+1)
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assign row_config[i] = config_bits[i*BITS_PER_ROW +: BITS_PER_ROW];
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end
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////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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// Inputs to the ROM muxes
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/*
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64:54 First group (left side, next to VCCINT rail)
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53:43 Second group
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42:32 Third group
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31:21 Fourth group
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20:10 Fifth group
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9:0 Sixth group (rightmost)
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*/
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wire[65:0] zbus =
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{
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macrocell_in,
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ibuf_in[31:16],
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dedicated_in,
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ibuf_in[15:0]
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};
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////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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// The ROM muxes (M3-M4 vias)
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//This is for the XC2C32A only
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//TODO: do other densities
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wire[7:0] zia_row_inputs[39:0];
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assign zia_row_inputs[0] = {2'b10, zbus[58], zbus[46], zbus[34], zbus[22], zbus[10], zbus[0]};
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assign zia_row_inputs[1] = {2'b10, zbus[61], zbus[48], zbus[41], zbus[23], zbus[11], zbus[1]};
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assign zia_row_inputs[2] = {2'b10, zbus[60], zbus[53], zbus[35], zbus[30], zbus[12], zbus[2]};
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assign zia_row_inputs[3] = {2'b10, zbus[55], zbus[47], zbus[42], zbus[26], zbus[13], zbus[3]};
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assign zia_row_inputs[4] = {2'b10, zbus[59], zbus[44], zbus[38], zbus[28], zbus[14], zbus[4]};
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assign zia_row_inputs[5] = {2'b10, zbus[56], zbus[50], zbus[40], zbus[31], zbus[15], zbus[5]};
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assign zia_row_inputs[6] = {2'b10, zbus[62], zbus[52], zbus[33], zbus[21], zbus[16], zbus[6]};
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assign zia_row_inputs[7] = {2'b10, zbus[64], zbus[45], zbus[32], zbus[27], zbus[17], zbus[7]};
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assign zia_row_inputs[8] = {2'b10, zbus[57], zbus[43], zbus[39], zbus[25], zbus[18], zbus[8]};
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assign zia_row_inputs[9] = {2'b10, zbus[54], zbus[51], zbus[37], zbus[24], zbus[19], zbus[9]};
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assign zia_row_inputs[10] = {2'b10, zbus[63], zbus[49], zbus[36], zbus[29], zbus[20], zbus[7]};
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assign zia_row_inputs[11] = {2'b10, zbus[59], zbus[47], zbus[35], zbus[23], zbus[11], zbus[0]};
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assign zia_row_inputs[12] = {2'b10, zbus[64], zbus[50], zbus[37], zbus[30], zbus[12], zbus[1]};
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assign zia_row_inputs[13] = {2'b10, zbus[62], zbus[49], zbus[42], zbus[24], zbus[19], zbus[2]};
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assign zia_row_inputs[14] = {2'b10, zbus[61], zbus[44], zbus[36], zbus[31], zbus[15], zbus[3]};
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assign zia_row_inputs[15] = {2'b10, zbus[56], zbus[48], zbus[33], zbus[27], zbus[17], zbus[4]};
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assign zia_row_inputs[16] = {2'b10, zbus[60], zbus[45], zbus[39], zbus[29], zbus[20], zbus[5]};
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assign zia_row_inputs[17] = {2'b10, zbus[57], zbus[51], zbus[41], zbus[22], zbus[10], zbus[6]};
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assign zia_row_inputs[18] = {2'b10, zbus[63], zbus[53], zbus[34], zbus[21], zbus[16], zbus[7]};
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assign zia_row_inputs[19] = {2'b10, zbus[55], zbus[46], zbus[32], zbus[28], zbus[14], zbus[8]};
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assign zia_row_inputs[20] = {2'b10, zbus[58], zbus[43], zbus[40], zbus[26], zbus[13], zbus[9]};
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assign zia_row_inputs[21] = {2'b10, zbus[54], zbus[52], zbus[38], zbus[25], zbus[18], zbus[8]};
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assign zia_row_inputs[22] = {2'b10, zbus[60], zbus[48], zbus[36], zbus[24], zbus[12], zbus[0]};
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assign zia_row_inputs[23] = {2'b10, zbus[54], zbus[53], zbus[39], zbus[26], zbus[19], zbus[1]};
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assign zia_row_inputs[24] = {2'b10, zbus[55], zbus[51], zbus[38], zbus[31], zbus[13], zbus[2]};
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assign zia_row_inputs[25] = {2'b10, zbus[63], zbus[50], zbus[33], zbus[25], zbus[20], zbus[3]};
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assign zia_row_inputs[26] = {2'b10, zbus[62], zbus[45], zbus[37], zbus[22], zbus[16], zbus[4]};
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assign zia_row_inputs[27] = {2'b10, zbus[57], zbus[49], zbus[34], zbus[28], zbus[18], zbus[5]};
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assign zia_row_inputs[28] = {2'b10, zbus[61], zbus[46], zbus[40], zbus[30], zbus[11], zbus[6]};
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assign zia_row_inputs[29] = {2'b10, zbus[58], zbus[52], zbus[42], zbus[23], zbus[10], zbus[7]};
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assign zia_row_inputs[30] = {2'b10, zbus[64], zbus[44], zbus[35], zbus[21], zbus[17], zbus[8]};
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assign zia_row_inputs[31] = {2'b10, zbus[56], zbus[47], zbus[32], zbus[29], zbus[15], zbus[9]};
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assign zia_row_inputs[32] = {2'b10, zbus[59], zbus[43], zbus[41], zbus[27], zbus[14], zbus[9]};
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assign zia_row_inputs[33] = {2'b10, zbus[61], zbus[49], zbus[37], zbus[25], zbus[13], zbus[0]};
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assign zia_row_inputs[34] = {2'b10, zbus[60], zbus[43], zbus[42], zbus[28], zbus[15], zbus[1]};
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assign zia_row_inputs[35] = {2'b10, zbus[54], zbus[44], zbus[40], zbus[27], zbus[20], zbus[2]};
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assign zia_row_inputs[36] = {2'b10, zbus[56], zbus[52], zbus[39], zbus[22], zbus[14], zbus[3]};
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assign zia_row_inputs[37] = {2'b10, zbus[64], zbus[51], zbus[34], zbus[26], zbus[11], zbus[4]};
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assign zia_row_inputs[38] = {2'b10, zbus[63], zbus[46], zbus[38], zbus[23], zbus[17], zbus[5]};
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assign zia_row_inputs[39] = {2'b10, zbus[58], zbus[50], zbus[35], zbus[29], zbus[19], zbus[6]};
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////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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// The SRAM muxes
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always @(*) begin
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for(i=0; i<40; i=i+1) begin
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//The real silicon uses a tristate mux so bus fights are possible if multiple bits are asserted.
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//For the FPGA model, use an if/else cascade to resolve ambiguity (rather than bus fight)
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//Note that bit 7 is active high but the rest are active low.
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//This is done to ensure that a blank bitstream (all 1s) puts the chip in a sane state.
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//TODO: model OGATE properly during the config step?
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if(row_config[i][7])
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zia_out[i] <= zia_row_inputs[i][7];
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else if(!row_config[i][6])
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zia_out[i] <= zia_row_inputs[i][6];
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else if(!row_config[i][5])
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zia_out[i] <= zia_row_inputs[i][5];
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else if(!row_config[i][4])
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zia_out[i] <= zia_row_inputs[i][4];
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else if(!row_config[i][3])
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zia_out[i] <= zia_row_inputs[i][3];
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else if(!row_config[i][2])
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zia_out[i] <= zia_row_inputs[i][2];
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else if(!row_config[i][1])
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zia_out[i] <= zia_row_inputs[i][1];
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else if(!row_config[i][0])
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zia_out[i] <= zia_row_inputs[i][0];
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//Default to 0 if no bits are active.
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//The real silicon has a weak keeper circuit for this
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else
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zia_out[i] <= 0;
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end
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end
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endmodule

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