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azonenbergazonenberg
committedMay 21, 2017
Added initial CoolRunner-II bitstream notes (from new RE + legacy crowbar code)
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‎doc/xbr/notes.txt

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========================================================================================================================
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XC2C32A (JED file bit ordering)
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========================================================================================================================
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CONVENTIONS
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-------------------------
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Leftmost bit in a row is MSB (N), rightmost is LSB (0)
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ZIA
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-------------------------
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320 bits starting at fuse # 0 (FB0), 6128 (FB1)
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40 rows, 8 bits per row
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Each row is an 8:1 one-hot mux. Inputs are active-low except for bit 7, which is active high.
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This is done so that the all-ones reset state is a constant, low-power value.
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7 Constant 1 (active HIGH)
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6 Constant 0
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5:0 Six inputs chosen from the six 11-bit muxes on metal 4
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PLA AND
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-------------------------
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4480 bits starting at fuse # 320 (FB0), 6448 (FB1)
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56 rows, 80 bits per row
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Each row configures inputs to an 80-input AND gate. 0 selects the signal, 1 selects a constant one.
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Each column corresponds to one ZIA output.
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TODO discuss bit ordering
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PLA OR
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-------------------------
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896 bits starting at fuse # 4800 (FB0), 10928 (FB1)
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56 rows, 16 bits per row
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Each column configures inputs to a 16-input OR gate. 0 selects the signal, 1 selects a constant zero.
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Each row corresponds to one product term.
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TODO discuss bit ordering
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Macrocells
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-------------------------
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432 bits starting at fuse # 5696 (FB0), 11824 (FB2)
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16 rows, 27 bits per row
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26 Selects input to the "11" clock source mux
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0 = Product Term Clock
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1 = Control Term Clock
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25 1 if FF is falling edge triggered, 0 if rising
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24:23 Clock source for the FF
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00 = GCK0
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01 = GCK1
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10 = GCK2
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11 = Product Term C or Control Term Clock
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22 1 if FF is DDR clocked, 0 if SDR
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21:20 Reset source for the FF
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00 = Product Term A
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01 = Global Set/Reset
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10 = Control Term Reset
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11 = disabled
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19:18 Set source for the FF
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00 = Product Term A
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01 = Global Set/Reset
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10 = Control Term Set
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11 = disabled
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17:16 Flipflop mode
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00 = D flipflop
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01 = latch
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10 = T flipflop
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11 = D flipflop with clock enable
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15:14 Input mux of some sort
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00 = input to ZIA
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11 = unused input
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Other values unknown
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13:12 "FB val" - no idea what this is yet
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11 Selects input to the flipflop
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0 = input buffer
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1 = XOR gate from PLA
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10 Schmitt trigger enable
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0 = normal
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1 = Schmitt trigger
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9:8 XOR gate input mux
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00 = Constant zero (pass-through of OR array)
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01 = Complement of product term C
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10 = Product term C
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11 = Constant one (invert output of OR array)
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7 Output buffer input source
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0 = Flipflop
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1 = XOR gate output
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6:3 Output enable / mode
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0000 Push-pull output
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0001 Open-drain output
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1000 Tri-state output
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1110 CGND (drive constant zero to reduce ground bounce?)
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1111 Floating (used for inputs)
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Other values unknown
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2 Termination mode
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0 = Float
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1 = Pullup / bus keeper active
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1 Slew rate
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0 = fast
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1 = slow
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0 Power-up state of flipflop (inverted)
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0 = initialize to 1
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1 = initialize to 0
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Global clock mux
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-------------------------
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3 bits starting at fuse # 12256
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0 = not used
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1 = used
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2 GCK0
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1 GCK1
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0 GCK2
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Global set/reset mux
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-------------------------
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2 bits starting at fuse # 12259
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Most likely one controls GS and one GR but not yet known which is which
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Global OE mux
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-------------------------
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8 bits starting at fuse # 12261
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Unknown functionality, but related to I/O cells somehow
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Global termination mode
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-------------------------
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Fuse # 12269
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0 Bus hold
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1 Pull-up
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Legacy I/O standard config (for XC2C32A bitstream compatibility)
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-------------------------
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2 bits starting at fuse # 12270
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1 Output voltage
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0 Input voltage
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Both are always 1 in XC2C32A bitstreams. Seems like they're probably ORed with bank I/O config?
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Dedicated input mode
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-------------------------
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2 bits starting at fuse # 12272
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Unknown functionality, but related to the input-only pin (not on a macrocell)
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Per-bank I/O standard config
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-------------------------
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4 bits starting at fuse # 12274
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3 Bank 0 input voltage
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2 Bank 0 output voltage
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1 Bank 1 input voltage
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0 Bank 1 output voltage
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Meaning of each bit:
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0 High voltage (LVTTL, LVCMOS33, or LVCMOS25)
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1 Low voltage (LVCMOS18 or LVCMOS15)
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It's unclear why there's separate values for input and output; so far it appears they always have the same value.
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Special product terms
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-------------------------
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Some product terms have special functionality beyond their use as general logic.
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All product term and function block indexes are zero based.
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Control term set: 6
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Control term reset: 5
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Control term clock: 4
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Control term enable: 7 (conjecture)
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Product term A: 3N + 8
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Product term B: 3N + 9 (conjecture)
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Product term C: 3N + 10

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