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  • 3 commits
  • 1 file changed
  • 1 contributor

Commits on May 21, 2017

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  3. Documented mask mux bit 4

    azonenberg committed May 21, 2017
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Showing with 58 additions and 5 deletions.
  1. +58 −5 doc/xbr/notes.txt
63 changes: 58 additions & 5 deletions doc/xbr/notes.txt
Original file line number Diff line number Diff line change
@@ -10,21 +10,62 @@ ZIA
-------------------------
320 bits starting at fuse # 0 (FB0), 6128 (FB1)
40 rows, 8 bits per row
Each row is an 8:1 one-hot mux. Inputs are active-low except for bit 7, which is active high.
Each row is an 65:1 mux corresponding to one output from the global routing matrix.
The mux is a two level tree.
The first level consists of six 11:1 mask-programmed muxes (with a different coding for each row), reducing the 65
signals on the metal 4 bus down to six. The second level is an 8:1 one-hot bitstream-programmed mux, which selects the
final routing output as either a constant value or one of the six mask mux outputs.

Mask ROM mux inputs:
Bit 5:
FB1 macrocell 15 (row 7, 12, 30, 37)
FB1 macrocell 14 (row 10, 18, 25, 38)
FB1 macrocell 13 (row 6, 13, 26)
FB1 macrocell 12 (row 1, 14, 28, 33)
FB1 macrocell 11 (row 2, 16, 22, 34)
FB1 macrocell 10 (row 4, 11, 32)
FB1 macrocell 9 (row 0, 20, 29, 39)
FB1 macrocell 8 (row 8, 17, 27)
FB1 macrocell 7 (row 5, 15, 31, 36)
FB1 macrocell 6 (row 3, 19, 24)
FB1 macrocell 5 (row 9, 21, 23, 35)
Bit 4:
FB1 macrocell 4 (row 2, 18, 23)
FB1 macrocell 3 (row 6, 21, 29, 36)
FB1 macrocell 2 (row 9, 17, 24, 37)
FB1 macrocell 1 (row 5, 12, 25, 39)
FB1 macrocell 0 (row 10, 13, 27, 33)
FB0 macrocell 15 (row 1, 15, 22)
FB0 macrocell 14 (row 3, 11, 31)
FB0 macrocell 13 (row 0, 19, 28, 38)
FB0 macrocell 12 (row 7, 16, 26)
FB0 macrocell 11 (row 4, 14, 30, 35)
FB0 macrocell 10 (row 8, 20, 32, 34)
Bit 3:
Bit 2:
Bit 1:

Bitstream mux inputs:
Inputs are active-low except for bit 7, which is active high.
This is done so that the all-ones reset state is a constant, low-power value.
7 Constant 1 (active HIGH)
6 Constant 0
5:0 Six inputs chosen from the six 11-bit muxes on metal 4
5:0 Mask-programmed mux outputs

PLA AND
-------------------------

4480 bits starting at fuse # 320 (FB0), 6448 (FB1)
56 rows, 80 bits per row
Each row configures inputs to an 80-input AND gate. 0 selects the signal, 1 selects a constant one.
Each column corresponds to one ZIA output.
First row is product term #0, second row product term #1, etc

TODO discuss bit ordering
Bit ordering for each row:
0 ZIA row #0 non-inverted output
1 ZIA row #0 inverted output
2 ZIA row #1 non-inverted output
3 ZIA row #1 inverted output
...

PLA OR
-------------------------
@@ -33,7 +74,19 @@ PLA OR
Each column configures inputs to a 16-input OR gate. 0 selects the signal, 1 selects a constant zero.
Each row corresponds to one product term.

TODO discuss bit ordering
Bit ordering for columns:
0 Macrocell 15
1 Macrocell 14
...
14 Macrocell 1
15 Macrocell 0

Bit ordering for rows
0 Product term 0
1 Product term 1
...
54 Product term 54
55 Product term 55

Macrocells
-------------------------