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Began work on DAC-from-counter support. See #32
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azonenberg committed May 22, 2017
1 parent e2fb1f1 commit 2667f1b
Showing 4 changed files with 41 additions and 11 deletions.
14 changes: 9 additions & 5 deletions doc/gp4-hdl.tex
Original file line number Diff line number Diff line change
@@ -806,9 +806,9 @@ \subsection{Counters}
\namestyle{Yosys} provides limited inference capability for counters which match the capabilities of the hard macro counters
(\tokenref{GP\_COUNT8}{gp-count8} and \tokenref{GP\_COUNT14}{gp-count14}) in the device.

Some hard macro capabilities (most notably input dividers) are not yet supported for inference; if these capabilities
are required then use explicit primitive instantiation. Future software releases will expand the set of counter
features which may be inferred.
Some hard macro capabilities (most notably input dividers and parallel output to DCMP/DAC blocks) are not yet supported
for inference; if these capabilities are required then use explicit primitive instantiation. Future software releases
will expand the set of counter features which may be inferred.

\subsubsection{Inference Requirements}

@@ -819,7 +819,8 @@ \subsubsection{Inference Requirements}
\item Count down only
\item Be initialized to the same (maximum) value by both underflow and by power-on reset
\item Have either no reset, or a positive level triggered reset to zero
\item Not have any logic use the internal counter register. Only the ``underflow" signal may be used by surrounding logic.
\item Not have any logic use the internal counter register. Only the ``underflow" signal may be used by surrounding
logic.
\end{itemize}

\subsubsection{Counter Related Constraints}
@@ -1736,13 +1737,16 @@ \subsubsection{Introduction}
This primitive corresponds to an 8-bit digital to analog converter. The DAC operates combinatorially and does not
require a clock.

Note that the DAC's input uses dedicated routing and not a general fabric connection; see the device datasheet for
information on legal connections.

\subsubsection{Port Descriptions}

\begin{tabularx}{\textwidth}{lllX}
\thinhline
\whenstyle{Port} & \whenstyle{Type} & \whenstyle{Width} & \whenstyle{Function} \\
\thickhline
\tokenstyle{DIN} & Input & 8 & Input data. Must be connected to an 8-bit constant value for now. \\
\tokenstyle{DIN} & Input & 8 & Input data. \\
\thinhline
\tokenstyle{VREF} & Input & 1 & Analog reference voltage from \tokenref{GP\_VREF}{gp-vref}. \\
\thinhline
12 changes: 11 additions & 1 deletion src/gp4par/make_graphs.cpp
Original file line number Diff line number Diff line change
@@ -1259,7 +1259,17 @@ void MakeDeviceEdges(Greenpak4Device* device)
gnd->AddEdge("OUT", dac, "DIN[7]");
}

//TODO: Direct inputs from counters
//Add inputs from counters to each DAC (shared with DCMP mux)
for(size_t j=0; j<device->GetDACCount(); j++)
{
auto dac = device->GetDAC(j)->GetPARNode();
for(int i=0; i<8; i++)
{
snprintf(inname, sizeof(inname), "DIN[%d]", i);
cnodes[9]->AddEdge("POUT", dac, inname);
cnodes[2]->AddEdge("POUT", dac, inname);
}
}

////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// OUTPUTS FROM DAC
6 changes: 3 additions & 3 deletions src/greenpak4/Greenpak4DAC.cpp
Original file line number Diff line number Diff line change
@@ -185,13 +185,13 @@ bool Greenpak4DAC::Save(bool* bitstream)
if(m_device->GetPart() == Greenpak4Device::GREENPAK4_SLG46140)
LogError("Greenpak4DAC: not implemented for 46140 yet\n");

//Input selector (hard code to "register" for now)
//Input selector
//WTF, the config is flipped from DAC0 to DAC1??? (see SLG46620V table 40)
//This also applies to the SLG46140 (see SLG46140 table 28).
if(m_dacnum == 0)
bitstream[m_cbaseInsel] = false;
bitstream[m_cbaseInsel] = !dinPower;
else
bitstream[m_cbaseInsel] = true;
bitstream[m_cbaseInsel] = dinPower;

//Constant input voltage
if(dinPower)
20 changes: 18 additions & 2 deletions tests/greenpak4/slg46620v/Dac.v
Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
/***********************************************************************************************************************
* Copyright (C) 2016 Andrew Zonenberg and contributors *
* Copyright (C) 2017 Andrew Zonenberg and contributors *
* *
* This program is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser General *
* Public License as published by the Free Software Foundation; either version 2.1 of the License, or (at your option) *
@@ -98,6 +98,8 @@ module Dac(bg_ok, vout, vout2, wave_sync);

localparam COUNT_MAX = 255;

//TODO: support for inference of counters with parallel output
/*
(* LOC = "COUNT8_6" *)
(* COUNT_EXTRACT = "FORCE" *)
reg[7:0] count = COUNT_MAX;
@@ -110,14 +112,28 @@ module Dac(bg_ok, vout, vout2, wave_sync);
//Counter overflow signal to LED
assign wave_sync = (count == 0);
*/

//Explicitly instantiated counter b/c we don't yet have inference support when using POUT
wire[7:0] count_pout;
GP_COUNT8 #(
.CLKIN_DIVIDE(1),
.COUNT_TO(COUNT_MAX),
.RESET_MODE("RISING")
) cnt (
.CLK(clk_108hz),
.RST(1'b0),
.OUT(wave_sync),
.POUT(count_pout)
);

////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// DAC driving the voltage reference

wire vdac;
(* LOC = "DAC_1" *)
GP_DAC dac(
.DIN(8'hff), //count
.DIN(count_pout),
.VOUT(vdac),
.VREF(vref_1v0)
);

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