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Initial work on CoolRunner-II device simulation model
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azonenberg committed Jun 13, 2017
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96 changes: 96 additions & 0 deletions hdl/xc2c-model/XC2CDevice.v
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/***********************************************************************************************************************
* Copyright (C) 2016-2017 Andrew Zonenberg and contributors *
* *
* This program is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser General *
* Public License as published by the Free Software Foundation; either version 2.1 of the License, or (at your option) *
* any later version. *
* *
* This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied *
* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for *
* more details. *
* *
* You should have received a copy of the GNU Lesser General Public License along with this program; if not, you may *
* find one here: *
* https://www.gnu.org/licenses/old-licenses/lgpl-2.1.txt *
* or you may search the http://www.gnu.org website for the version 2.1 license, or you may write to the Free Software *
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA *
**********************************************************************************************************************/

/**
@brief Top level module for an XC2C-series device
*/
module XC2CDevice(
jtag_tdi, jtag_tms, jtag_tck, jtag_tdo,
dedicated_input, macrocell_io);

////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Device configuration

parameter MACROCELLS = 32; //A variant implied for 32/64, no support for base version

////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Helpers for figuring out dimensions etc of the device

function integer ConfigMemoryWidth(integer cells)
case(cells)
32: ConfigMemoryWidth <= 260;
default: ConfigMemoryWidth <= 0;
endcase
endfunction

function integer ConfigMemoryDepth(integer cells)
case(cells)
32: ConfigMemoryDepth <= 49;
default: ConfigMemoryDepth <= 0;
endcase
endfunction

localparam SHREG_WIDTH = ConfigMemoryWidth(MACROCELLS);
localparam MEM_DEPTH = ConfigMemoryDepth(MACROCELLS);

////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// I/Os

input wire jtag_tdi;
input wire jtag_tms;
input wire jtag_tck;
output wire jtag_tdo;

input wire dedicated_input; //only present in 32a

inout wire[MACROCELLS-1:0] macrocell_io; //The actual device I/O pins.
//Note that not all of these are broken out to bond pads;
//buried macrocells drive a constant 0 here

////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// The SRAM copy of the config bitstream (directly drives device behavior)

reg[SHREG_WIDTH-1:0] ram_bitstream[MEM_DEPTH-1:0];

integer i;
initial begin
for(i=0; i<MEM_DEPTH; i++)
ram_bitstream[i] <= {SHREG_WIDTH{1'b1}}; //copied from blank EEPROM = all 1s
end

////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// The EEPROM copy of the config bitstream (used to configure ram_bitstream at startup)

//TODO

////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// JTAG stuff

XC2CJTAG #(
.MACROCELLS(MACROCELLS)
) jtag (
.tdi(jtag_tdi),
.tdo(jtag_tdo),
.tms(jtag_tms),
.tck(jtag_tck)
);

////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// The actual CPLD function blocks

endmodule
206 changes: 206 additions & 0 deletions hdl/xc2c-model/XC2CJTAG.v
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/***********************************************************************************************************************
* Copyright (C) 2016-2017 Andrew Zonenberg and contributors *
* *
* This program is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser General *
* Public License as published by the Free Software Foundation; either version 2.1 of the License, or (at your option) *
* any later version. *
* *
* This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied *
* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for *
* more details. *
* *
* You should have received a copy of the GNU Lesser General Public License along with this program; if not, you may *
* find one here: *
* https://www.gnu.org/licenses/old-licenses/lgpl-2.1.txt *
* or you may search the http://www.gnu.org website for the version 2.1 license, or you may write to the Free Software *
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA *
**********************************************************************************************************************/

/**
@brief JTAG stuff for an XC2C-series device
*/
module XC2CJTAG(tdi, tms, tck, tdo);

////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Device configuration

parameter MACROCELLS = 32; //A variant implied for 32/64, no support for base version

////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// I/Os

input wire tdi;
input wire tms;
input wire tck;
output wire tdo;

////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// The core JTAG state machine

localparam STATE_TEST_LOGIC_RESET = 4'h0;
localparam STATE_RUN_TEST_IDLE = 4'h1;
localparam STATE_SELECT_DR_SCAN = 4'h2;
localparam STATE_SELECT_IR_SCAN = 4'h3;
localparam STATE_CAPTURE_DR = 4'h4;
localparam STATE_CAPTURE_IR = 4'h5;
localparam STATE_SHIFT_DR = 4'h6;
localparam STATE_SHIFT_IR = 4'h7;
localparam STATE_EXIT1_DR = 4'h8;
localparam STATE_EXIT1_IR = 4'h9;
localparam STATE_PAUSE_DR = 4'ha;
localparam STATE_PAUSE_IR = 4'hb;
localparam STATE_EXIT2_DR = 4'hc;
localparam STATE_EXIT2_IR = 4'hd;
localparam STATE_UPDATE_DR = 4'he;
localparam STATE_UPDATE_IR = 4'hf;

reg[3:0] state = STATE_TEST_LOGIC_RESET;

always @(posedge tck) begin

case(state)

STATE_TEST_LOGIC_RESET: begin
if(tms)
state <= STATE_RUN_TEST_IDLE;
end //end STATE_TEST_LOGIC_RESET

STATE_RUN_TEST_IDLE: begin
if(tms)
state <= STATE_SELECT_DR_SCAN;
end //end STATE_RUN_TEST_IDLE

STATE_SELECT_DR_SCAN: begin
if(tms)
state <= STATE_SELECT_IR_SCAN;
else
state <= STATE_CAPTURE_DR;
end //end STATE_SELECT_DR_SCAN

STATE_SELECT_IR_SCAN: begin
if(tms)
state <= STATE_TEST_LOGIC_RESET;
else
state <= STATE_CAPTURE_IR;
end //end STATE_SELECT_IR_SCAN

STATE_CAPTURE_DR: begin
if(tms)
state <= STATE_EXIT1_DR;
else
state <= STATE_SHIFT_DR;
end //end STATE_CAPTURE_DR

STATE_CAPTURE_IR: begin
if(tms)
state <= STATE_EXIT1_IR;
else
state <= STATE_SHIFT_IR;
end //end STATE_CAPTURE_IR

STATE_SHIFT_DR: begin
if(tms)
state <= STATE_EXIT1_DR;
end //end STATE_SHIFT_DR

STATE_SHIFT_IR: begin
if(tms)
state <= STATE_EXIT1_IR;
end //end STATE_SHIFT_IR

STATE_EXIT1_DR: begin
if(tms)
state <= STATE_UPDATE_DR;
else
state <= STATE_PAUSE_DR;
end //end STATE_EXIT1_DR

STATE_EXIT1_IR: begin
if(tms)
state <= STATE_UPDATE_IR;
else
state <= STATE_PAUSE_IR;
end //end STATE_EXIT1_IR

STATE_PAUSE_DR: begin
if(tms)
state <= STATE_EXIT2_DR;
end //end STATE_PAUSE_DR

STATE_PAUSE_IR: begin
if(tms)
state <= STATE_EXIT2_IR;
end //end STATE_PAUSE_IR

STATE_EXIT2_DR: begin
if(tms)
state <= STATE_UPDATE_DR;
else
state <= STATE_SHIFT_DR;
end //end STATE_EXIT2_DR

STATE_EXIT2_IR: begin
if(tms)
state <= STATE_UPDATE_IR;
else
state <= STATE_SHIFT_IR;
end //end STATE_EXIT2_IR

STATE_UPDATE_DR: begin
if(tms)
state <= STATE_SELECT_DR_SCAN;
else
state <= STATE_RUN_TEST_IDLE;
end //end STATE_UPDATE_DR

STATE_UPDATE_IR: begin
if(tms)
state <= STATE_SELECT_IR_SCAN;
else
state <= STATE_RUN_TEST_IDLE;
end //end STATE_UPDATE_IR

endcase

end

////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// The instruction register

localparam INST_BYPASS = 8'hff;
localparam INST_ISC_ENABLE = 8'he8;
localparam INST_ISC_ENABLEOTF = 8'he4;
localparam INST_ISC_SRAM_READ = 8'he7;
localparam INST_ISC_SRAM_WRITE = 8'he6;
localparam INST_ISC_ERASE = 8'hed;
localparam INST_ISC_PROGRAM = 8'hea;
localparam INST_ISC_INIT = 8'hf0;
localparam INST_ISC_DISABLE = 8'hc0;
localparam INST_ISC_READ = 8'hee;

/*
//TODO: implement some of these?
"INTEST (00000010)," &
"SAMPLE (00000011)," &
"EXTEST (00000000)," &
"IDCODE (00000001)," &
"USERCODE (11111101)," &
"HIGHZ (11111100)," &
"ISC_ENABLE_CLAMP (11101001)," &
"TEST_ENABLE (00010001)," &
"BULKPROG (00010010)," &
"ERASE_ALL (00010100)," &
"MVERIFY (00010011)," &
"TEST_DISABLE (00010101)," &
"ISC_NOOP (11100000)";
*/

reg[7:0] ir = INST_BYPASS;

//Capture stuff

////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// IDCODE DR

endmodule

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