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base repository: azonenberg/openfpga
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head repository: azonenberg/openfpga
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compare: 03e0c4b6a5b5
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  • 11 commits
  • 125 files changed
  • 1 contributor

Commits on Jun 12, 2017

  1. xc2bit: Fix 512-MC io standard

    Apparently this part has the bits inverted compared to the other parts
    ArcaneNibble committed Jun 12, 2017
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Showing with 398,444 additions and 132 deletions.
  1. +2 −2 src/xc2bit/reftests/128-clocks.txt
  2. +2 −2 src/xc2bit/reftests/128-dg.txt
  3. +1,393 −0 src/xc2bit/reftests/128-fb.jed
  4. +3,420 −0 src/xc2bit/reftests/128-fb.txt
  5. +1,393 −0 src/xc2bit/reftests/128-inmod.jed
  6. +3,420 −0 src/xc2bit/reftests/128-inmod.txt
  7. +1,393 −0 src/xc2bit/reftests/128-inreg.jed
  8. +3,420 −0 src/xc2bit/reftests/128-inreg.txt
  9. +1,393 −0 src/xc2bit/reftests/128-inz.jed
  10. +3,420 −0 src/xc2bit/reftests/128-inz.txt
  11. +1,393 −0 src/xc2bit/reftests/128-oe.jed
  12. +3,420 −0 src/xc2bit/reftests/128-oe.txt
  13. +2 −2 src/xc2bit/reftests/128-pu-buried.txt
  14. +2 −2 src/xc2bit/reftests/128-pu.txt
  15. +1,393 −0 src/xc2bit/reftests/128-regcom.jed
  16. +3,420 −0 src/xc2bit/reftests/128-regcom.txt
  17. +1,393 −0 src/xc2bit/reftests/128-regmod.jed
  18. +3,420 −0 src/xc2bit/reftests/128-regmod.txt
  19. +2 −2 src/xc2bit/reftests/128-setreset.txt
  20. +2 −2 src/xc2bit/reftests/128-slw.txt
  21. +2 −2 src/xc2bit/reftests/128-tm.txt
  22. +1,393 −0 src/xc2bit/reftests/128-xorin.jed
  23. +3,420 −0 src/xc2bit/reftests/128-xorin.txt
  24. +2 −2 src/xc2bit/reftests/256-clocks.txt
  25. +2 −2 src/xc2bit/reftests/256-dg.txt
  26. +2,769 −0 src/xc2bit/reftests/256-fb.jed
  27. +6,672 −0 src/xc2bit/reftests/256-fb.txt
  28. +2,769 −0 src/xc2bit/reftests/256-inmod.jed
  29. +6,672 −0 src/xc2bit/reftests/256-inmod.txt
  30. +2,769 −0 src/xc2bit/reftests/256-inreg.jed
  31. +6,672 −0 src/xc2bit/reftests/256-inreg.txt
  32. +2,769 −0 src/xc2bit/reftests/256-inz.jed
  33. +6,672 −0 src/xc2bit/reftests/256-inz.txt
  34. +2,769 −0 src/xc2bit/reftests/256-oe.jed
  35. +6,672 −0 src/xc2bit/reftests/256-oe.txt
  36. +2 −2 src/xc2bit/reftests/256-pu-buried.txt
  37. +2 −2 src/xc2bit/reftests/256-pu.txt
  38. +2,769 −0 src/xc2bit/reftests/256-regcom.jed
  39. +6,672 −0 src/xc2bit/reftests/256-regcom.txt
  40. +2,769 −0 src/xc2bit/reftests/256-regmod.jed
  41. +6,672 −0 src/xc2bit/reftests/256-regmod.txt
  42. +2 −2 src/xc2bit/reftests/256-setreset.txt
  43. +2 −2 src/xc2bit/reftests/256-slw.txt
  44. +2 −2 src/xc2bit/reftests/256-tm.txt
  45. +2,769 −0 src/xc2bit/reftests/256-xorin.jed
  46. +6,672 −0 src/xc2bit/reftests/256-xorin.txt
  47. +362 −0 src/xc2bit/reftests/32-fb.jed
  48. +904 −0 src/xc2bit/reftests/32-fb.txt
  49. +362 −0 src/xc2bit/reftests/32-inreg.jed
  50. +904 −0 src/xc2bit/reftests/32-inreg.txt
  51. +362 −0 src/xc2bit/reftests/32-inz.jed
  52. +904 −0 src/xc2bit/reftests/32-inz.txt
  53. +362 −0 src/xc2bit/reftests/32-oe.jed
  54. +904 −0 src/xc2bit/reftests/32-oe.txt
  55. +362 −0 src/xc2bit/reftests/32-regcom.jed
  56. +904 −0 src/xc2bit/reftests/32-regcom.txt
  57. +362 −0 src/xc2bit/reftests/32-regmod.jed
  58. +904 −0 src/xc2bit/reftests/32-regmod.txt
  59. +362 −0 src/xc2bit/reftests/32-st.jed
  60. +904 −0 src/xc2bit/reftests/32-st.txt
  61. +362 −0 src/xc2bit/reftests/32-xorin.jed
  62. +904 −0 src/xc2bit/reftests/32-xorin.txt
  63. +2 −2 src/xc2bit/reftests/384-clocks.txt
  64. +2 −2 src/xc2bit/reftests/384-dg.txt
  65. +4,145 −0 src/xc2bit/reftests/384-fb.jed
  66. +9,676 −0 src/xc2bit/reftests/384-fb.txt
  67. +4,145 −0 src/xc2bit/reftests/384-inmod.jed
  68. +9,676 −0 src/xc2bit/reftests/384-inmod.txt
  69. +4,145 −0 src/xc2bit/reftests/384-inreg.jed
  70. +9,676 −0 src/xc2bit/reftests/384-inreg.txt
  71. +4,145 −0 src/xc2bit/reftests/384-inz.jed
  72. +9,676 −0 src/xc2bit/reftests/384-inz.txt
  73. +4,145 −0 src/xc2bit/reftests/384-oe.jed
  74. +9,676 −0 src/xc2bit/reftests/384-oe.txt
  75. +2 −2 src/xc2bit/reftests/384-pu-buried.txt
  76. +2 −2 src/xc2bit/reftests/384-pu.txt
  77. +4,145 −0 src/xc2bit/reftests/384-regcom.jed
  78. +9,676 −0 src/xc2bit/reftests/384-regcom.txt
  79. +4,145 −0 src/xc2bit/reftests/384-regmod.jed
  80. +9,676 −0 src/xc2bit/reftests/384-regmod.txt
  81. +2 −2 src/xc2bit/reftests/384-setreset.txt
  82. +2 −2 src/xc2bit/reftests/384-slw.txt
  83. +2 −2 src/xc2bit/reftests/384-tm.txt
  84. +4,145 −0 src/xc2bit/reftests/384-xorin.jed
  85. +9,676 −0 src/xc2bit/reftests/384-xorin.txt
  86. +10 −10 src/xc2bit/reftests/512-clocks.txt
  87. +10 −10 src/xc2bit/reftests/512-dg.txt
  88. +5,521 −0 src/xc2bit/reftests/512-fb.jed
  89. +12,442 −0 src/xc2bit/reftests/512-fb.txt
  90. +5,521 −0 src/xc2bit/reftests/512-inmod.jed
  91. +12,442 −0 src/xc2bit/reftests/512-inmod.txt
  92. +5,521 −0 src/xc2bit/reftests/512-inreg.jed
  93. +12,442 −0 src/xc2bit/reftests/512-inreg.txt
  94. +5,521 −0 src/xc2bit/reftests/512-inz.jed
  95. +12,442 −0 src/xc2bit/reftests/512-inz.txt
  96. +5,521 −0 src/xc2bit/reftests/512-oe.jed
  97. +12,442 −0 src/xc2bit/reftests/512-oe.txt
  98. +10 −10 src/xc2bit/reftests/512-pu-buried.txt
  99. +10 −10 src/xc2bit/reftests/512-pu.txt
  100. +5,521 −0 src/xc2bit/reftests/512-regcom.jed
  101. +12,442 −0 src/xc2bit/reftests/512-regcom.txt
  102. +5,521 −0 src/xc2bit/reftests/512-regmod.jed
  103. +12,442 −0 src/xc2bit/reftests/512-regmod.txt
  104. +10 −10 src/xc2bit/reftests/512-setreset.txt
  105. +10 −10 src/xc2bit/reftests/512-slw.txt
  106. +10 −10 src/xc2bit/reftests/512-tm.txt
  107. +5,521 −0 src/xc2bit/reftests/512-xorin.jed
  108. +12,442 −0 src/xc2bit/reftests/512-xorin.txt
  109. +705 −0 src/xc2bit/reftests/64-fb.jed
  110. +1,780 −0 src/xc2bit/reftests/64-fb.txt
  111. +705 −0 src/xc2bit/reftests/64-inreg.jed
  112. +1,780 −0 src/xc2bit/reftests/64-inreg.txt
  113. +705 −0 src/xc2bit/reftests/64-inz.jed
  114. +1,780 −0 src/xc2bit/reftests/64-inz.txt
  115. +705 −0 src/xc2bit/reftests/64-oe.jed
  116. +1,780 −0 src/xc2bit/reftests/64-oe.txt
  117. +705 −0 src/xc2bit/reftests/64-regcom.jed
  118. +1,780 −0 src/xc2bit/reftests/64-regcom.txt
  119. +705 −0 src/xc2bit/reftests/64-regmod.jed
  120. +1,780 −0 src/xc2bit/reftests/64-regmod.txt
  121. +705 −0 src/xc2bit/reftests/64-st.jed
  122. +1,780 −0 src/xc2bit/reftests/64-st.txt
  123. +705 −0 src/xc2bit/reftests/64-xorin.jed
  124. +1,780 −0 src/xc2bit/reftests/64-xorin.txt
  125. +20 −20 src/xc2bit/src/bitstream.rs
4 changes: 2 additions & 2 deletions src/xc2bit/reftests/128-clocks.txt
Original file line number Diff line number Diff line change
@@ -6,8 +6,8 @@ bank 0 output voltage range: low
bank 1 output voltage range: low
bank 0 input voltage range: low
bank 1 input voltage range: low
DataGate used: low
VREF used: low
DataGate used: no
VREF used: no

GCK2 clock divider disabled
clock divider delay disabled
4 changes: 2 additions & 2 deletions src/xc2bit/reftests/128-dg.txt
Original file line number Diff line number Diff line change
@@ -6,8 +6,8 @@ bank 0 output voltage range: low
bank 1 output voltage range: low
bank 0 input voltage range: low
bank 1 input voltage range: low
DataGate used: low
VREF used: low
DataGate used: no
VREF used: no

GCK2 clock divider disabled
clock divider delay disabled
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