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committedOct 25, 2017
ise: support cpld workflow
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+18
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Diff for: ‎migen/build/xilinx/ise.py

+18-9
Original file line numberDiff line numberDiff line change
@@ -82,7 +82,7 @@ def _run_yosys(device, sources, vincpaths, build_name):
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8383

8484
def _run_ise(build_name, ise_path, source, mode, ngdbuild_opt,
85-
bitgen_opt, ise_commands, map_opt, par_opt, ver=None):
85+
toolchain, platform, ver=None):
8686
if sys.platform == "win32" or sys.platform == "cygwin":
8787
source_cmd = "call "
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script_ext = ".bat"
@@ -108,14 +108,24 @@ def _run_ise(build_name, ise_path, source, mode, ngdbuild_opt,
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build_script_contents += """
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ngdbuild {ngdbuild_opt} -uc {build_name}.ucf {build_name}.{ext} {build_name}.ngd{fail_stmt}
111+
"""
112+
if mode == "cpld":
113+
build_script_contents += """
114+
cpldfit -ofmt verilog {par_opt} -p {device} {build_name}.ngd{fail_stmt}
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taengine -f {build_name}.vm6 -detail -iopath -l {build_name}.tim{fail_stmt}
116+
hprep6 -s IEEE1532 -i {build_name}.vm6{fail_stmt}
117+
"""
118+
else:
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build_script_contents += """
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map {map_opt} -o {build_name}_map.ncd {build_name}.ngd {build_name}.pcf{fail_stmt}
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par {par_opt} {build_name}_map.ncd {build_name}.ncd {build_name}.pcf{fail_stmt}
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bitgen {bitgen_opt} {build_name}.ncd {build_name}.bit{fail_stmt}
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"""
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build_script_contents = build_script_contents.format(build_name=build_name,
116-
ngdbuild_opt=ngdbuild_opt, bitgen_opt=bitgen_opt, ext=ext,
117-
par_opt=par_opt, map_opt=map_opt, fail_stmt=fail_stmt)
118-
build_script_contents += ise_commands.format(build_name=build_name)
125+
ngdbuild_opt=ngdbuild_opt, bitgen_opt=toolchain.bitgen_opt, ext=ext,
126+
par_opt=toolchain.par_opt, map_opt=toolchain.map_opt,
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device=platform.device, fail_stmt=fail_stmt)
128+
build_script_contents += toolchain.ise_commands.format(build_name=build_name)
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build_script_file = "build_" + build_name + script_ext
120130
tools.write_to_file(build_script_file, build_script_contents, force_unix=False)
121131
command = shell + [build_script_file]
@@ -168,16 +178,16 @@ def build(self, platform, fragment, build_dir="build", build_name="top",
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cwd = os.getcwd()
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os.chdir(build_dir)
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try:
171-
if mode == "xst" or mode == "yosys":
181+
if mode in ("xst", "yosys", "cpld"):
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v_output = platform.get_verilog(fragment)
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vns = v_output.ns
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named_sc, named_pc = platform.resolve_signals(vns)
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v_file = build_name + ".v"
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v_output.write(v_file)
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sources = platform.sources | {(v_file, "verilog", "work")}
178-
if mode == "xst":
188+
if mode in ("xst", "cpld"):
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_build_xst_files(platform.device, sources, platform.verilog_include_paths, build_name, self.xst_opt)
180-
isemode = "xst"
190+
isemode = mode
181191
else:
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_run_yosys(platform.device, sources, platform.verilog_include_paths, build_name)
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isemode = "edif"
@@ -198,8 +208,7 @@ def build(self, platform, fragment, build_dir="build", build_name="top",
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tools.write_to_file(build_name + ".ucf", _build_ucf(named_sc, named_pc))
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if run:
200210
_run_ise(build_name, toolchain_path, source, isemode,
201-
ngdbuild_opt, self.bitgen_opt, self.ise_commands,
202-
self.map_opt, self.par_opt)
211+
ngdbuild_opt, self, platform)
203212
finally:
204213
os.chdir(cwd)
205214

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