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base repository: m-labs/migen
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head repository: m-labs/migen
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compare: 71a48446d9d4
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  • 2 commits
  • 2 files changed
  • 1 contributor

Commits on Nov 13, 2017

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    a728e6a View commit details
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    71a4844 View commit details
Showing with 55 additions and 0 deletions.
  1. +15 −0 migen/build/lattice/programmer.py
  2. +40 −0 migen/build/platforms/tinyfpga_b.py
15 changes: 15 additions & 0 deletions migen/build/lattice/programmer.py
Original file line number Diff line number Diff line change
@@ -37,3 +37,18 @@ def __init__(self, iceburn_path):

def load_bitstream(self, bitstream_file):
subprocess.call([self.iceburn, "-evw", bitstream_file])


class TinyFpgaBProgrammer(GenericProgrammer):
needs_bitreverse = False

# The default flash address you probably want is 0x30000; the image at
# address 0 is for the bootloader.
def flash(self, address, bitstream_file):
subprocess.call(["tinyfpgab", "-a", str(address), "-p",
bitstream_file])

# Force user image to boot if a user reset tinyfpga, the bootloader
# is active, and the user image need not be reprogrammed.
def boot(self):
subprocess.call(["tinyfpgab", "-b"])
40 changes: 40 additions & 0 deletions migen/build/platforms/tinyfpga_b.py
Original file line number Diff line number Diff line change
@@ -0,0 +1,40 @@
from migen.build.generic_platform import *
from migen.build.lattice import LatticePlatform
from migen.build.lattice.programmer import TinyFpgaBProgrammer

_io = [
("usb", 0,
Subsignal("d_p", Pins("A3")),
Subsignal("d_n", Pins("A4")),
IOStandard("LVCMOS33")
),

("spiflash", 0,
Subsignal("cs_n", Pins("F7"), IOStandard("LVCMOS33")),
Subsignal("clk", Pins("G7"), IOStandard("LVCMOS33")),
Subsignal("mosi", Pins("G6"), IOStandard("LVCMOS33")),
Subsignal("miso", Pins("H7"), IOStandard("LVCMOS33"))
),

("clk16", 0, Pins("B4"), IOStandard("LVCMOS33"))
]

_connectors = [
# B2-J1, Pins 4-13
# D9-C9, Pins 18-19, Pins 21-24
# E8, Pin 20 (Input only)
("GPIO", "B2 A2 A1 B1 C1 D1 E1 G1 H1 J1 D9 C9 A9 A8 A7 A6"),
("GBIN", "E8")
]


class Platform(LatticePlatform):
default_clk_name = "clk16"
default_clk_period = 62.5

def __init__(self):
LatticePlatform.__init__(self, "ice40-lp8k-cm81", _io, _connectors,
toolchain="icestorm")

def create_programmer(self):
return TinyFpgaBProgrammer()