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liteeth: add CRC error and dropped packet counters.
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whitequark committed Oct 30, 2017
1 parent 362de1a commit 9d3697c
Showing 3 changed files with 25 additions and 0 deletions.
11 changes: 11 additions & 0 deletions misoc/cores/liteeth_mini/mac/core.py
Original file line number Diff line number Diff line change
@@ -1,4 +1,5 @@
from migen import *
from migen.genlib.cdc import PulseSynchronizer

from misoc.interconnect.csr import *
from misoc.interconnect import stream
@@ -28,6 +29,8 @@ def __init__(self, phy, dw, endianness="big",
# Preamble / CRC
if with_preamble_crc:
self._preamble_crc = CSRStatus(reset=1)
self.crc_errors = CSRStatus(32)

# Preamble insert/check
preamble_inserter = preamble.LiteEthMACPreambleInserter(phy.dw)
preamble_checker = preamble.LiteEthMACPreambleChecker(phy.dw)
@@ -43,6 +46,14 @@ def __init__(self, phy, dw, endianness="big",
tx_pipeline += [preamble_inserter, crc32_inserter]
rx_pipeline += [preamble_checker, crc32_checker]

# CRC error counter
self.submodules.ps_crc_error = PulseSynchronizer("eth_rx", "sys")

self.comb += self.ps_crc_error.i.eq(crc32_checker.crc_error)
self.sync += [
If(self.ps_crc_error.o,
self.crc_errors.status.eq(self.crc_errors.status + 1))]

# Padding
if with_padding:
padding_inserter = padding.LiteEthMACPaddingInserter(phy.dw, 60)
9 changes: 9 additions & 0 deletions misoc/cores/liteeth_mini/mac/crc.py
Original file line number Diff line number Diff line change
@@ -216,11 +216,15 @@ class LiteEthMACCRCChecker(Module):
source : out
Packets output without CRC and "error" set to 0
on eop when CRC OK / set to 1 when CRC KO.
crc_error : out
Pulses every time a CRC error is detected.
"""
def __init__(self, crc_class, layout):
self.sink = sink = stream.Endpoint(layout)
self.source = source = stream.Endpoint(layout)

self.crc_error = Signal()

# # #

dw = len(sink.data)
@@ -255,6 +259,11 @@ def __init__(self, crc_class, layout):
source.error.eq(sink.error | crc.error),
]

crc_error_r = Signal()

self.comb += self.crc_error.eq(crc.error & ~crc_error_r)
self.sync += crc_error_r.eq(crc.error)

fsm.act("RESET",
crc.reset.eq(1),
fifo.reset.eq(1),
5 changes: 5 additions & 0 deletions misoc/cores/liteeth_mini/mac/sram.py
Original file line number Diff line number Diff line change
@@ -17,6 +17,8 @@ def __init__(self, dw, depth, nslots=2):
self._slot = CSRStatus(slotbits)
self._length = CSRStatus(lengthbits)

self.errors = CSRStatus(32)

self.submodules.ev = EventManager()
self.ev.available = EventSourceLevel()
self.ev.finalize()
@@ -69,6 +71,9 @@ def __init__(self, dw, depth, nslots=2):
ongoing.eq(1),
counter_ce.eq(1),
NextState("WRITE")
).Else(
NextValue(self.errors.status, self.errors.status + 1),
NextState("DISCARD_REMAINING")
)
)
)

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