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base repository: m-labs/misoc
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head repository: m-labs/misoc
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compare: 649d3eddbddd
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  • 2 commits
  • 2 files changed
  • 1 contributor

Commits on Nov 8, 2017

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    8083213 View commit details
  2. Copy the full SHA
    649d3ed View commit details
Showing with 2 additions and 2 deletions.
  1. +1 −1 misoc/cores/sdram_phy/kusddrphy.py
  2. +1 −1 misoc/targets/sayma_amc.py
2 changes: 1 addition & 1 deletion misoc/cores/sdram_phy/kusddrphy.py
Original file line number Diff line number Diff line change
@@ -196,7 +196,7 @@ def __init__(self, pads):
dq_bitslip = BitSlip(8)
self.sync += \
If(self._dly_sel.storage[i//8],
If(self._rdly_dq_rst.re,
If(self._wdly_dq_rst.re,
dq_bitslip.value.eq(0)
).Elif(self._rdly_dq_bitslip.re,
dq_bitslip.value.eq(dq_bitslip.value + 1)
2 changes: 1 addition & 1 deletion misoc/targets/sayma_amc.py
Original file line number Diff line number Diff line change
@@ -46,7 +46,7 @@ def __init__(self, platform):
p_CLKOUT1_DIVIDE=2, p_CLKOUT1_PHASE=0.0, o_CLKOUT1=pll_sys4x,

# 500MHz dqs
p_CLKOUT2_DIVIDE=2, p_CLKOUT2_PHASE=90.0, o_CLKOUT2=pll_sys4x_dqs,
p_CLKOUT2_DIVIDE=2, p_CLKOUT2_PHASE=45.0, o_CLKOUT2=pll_sys4x_dqs,

# 200MHz
p_CLKOUT3_DIVIDE=5, p_CLKOUT3_PHASE=0.0, o_CLKOUT3=pll_clk200