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base repository: m-labs/migen
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head repository: m-labs/migen
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compare: a79badb1d429
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  • 2 commits
  • 1 file changed
  • 1 contributor

Commits on Nov 8, 2017

  1. kasli: fix ddr3.a7

    jordens committed Nov 8, 2017
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    2e73dbd View commit details
  2. kasli: add internal VREF

    jordens committed Nov 8, 2017
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    a79badb View commit details
Showing with 3 additions and 1 deletion.
  1. +3 −1 migen/build/platforms/sinara/kasli.py
4 changes: 3 additions & 1 deletion migen/build/platforms/sinara/kasli.py
Original file line number Diff line number Diff line change
@@ -115,7 +115,7 @@

("ddram", 0,
Subsignal("a", Pins(
"L6 M5 P6 K6 M1 M3 N2 N7 "
"L6 M5 P6 K6 M1 M3 N2 M6 "
"P1 P2 L4 N5 L3 R1 N3"),
IOStandard("SSTL15")),
Subsignal("ba", Pins("L5 M2 N4"), IOStandard("SSTL15")),
@@ -173,3 +173,5 @@ def __init__(self):
XilinxPlatform.__init__(
self, "xc7a100t-fgg484-2", _io, _connectors,
toolchain="vivado")
self.add_platform_command(
"set_property INTERNAL_VREF 0.750 [get_iobanks 35]")