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base repository: m-labs/misoc
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head repository: m-labs/misoc
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compare: e52727a6965d
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  • 3 commits
  • 3 files changed
  • 1 contributor

Commits on Feb 11, 2017

  1. mor1kx: bump

    jordens committed Feb 11, 2017
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    bf8f100 View commit details
  2. Copy the full SHA
    bc43b76 View commit details

Commits on Feb 12, 2017

  1. mor1kx: bump

    jordens committed Feb 12, 2017
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    e52727a View commit details
Showing with 34 additions and 28 deletions.
  1. +31 −26 misoc/cores/mor1kx/core.py
  2. +1 −1 misoc/cores/mor1kx/verilog
  3. +2 −1 misoc/integration/soc_core.py
57 changes: 31 additions & 26 deletions misoc/cores/mor1kx/core.py
Original file line number Diff line number Diff line change
@@ -6,40 +6,43 @@


class MOR1KX(Module):
def __init__(self, platform, reset_pc):
def __init__(self, platform, **kwargs):
self.ibus = i = wishbone.Interface()
self.dbus = d = wishbone.Interface()
self.interrupt = Signal(32)

###

defaults = dict(
FEATURE_INSTRUCTIONCACHE="ENABLED",
OPTION_ICACHE_BLOCK_WIDTH=4,
OPTION_ICACHE_SET_WIDTH=8,
OPTION_ICACHE_WAYS=1,
OPTION_ICACHE_LIMIT_WIDTH=31,
FEATURE_DATACACHE="ENABLED",
OPTION_DCACHE_BLOCK_WIDTH=4,
OPTION_DCACHE_SET_WIDTH=8,
OPTION_DCACHE_WAYS=1,
OPTION_DCACHE_LIMIT_WIDTH=31,
FEATURE_TIMER="NONE",
OPTION_PIC_TRIGGER="LEVEL",
FEATURE_SYSCALL="NONE",
FEATURE_TRAP="NONE",
FEATURE_RANGE="NONE",
FEATURE_OVERFLOW="NONE",
FEATURE_ADDC="ENABLED",
FEATURE_CMOV="ENABLED",
FEATURE_FFL1="ENABLED",
OPTION_CPU0="CAPPUCCINO",
IBUS_WB_TYPE="B3_REGISTERED_FEEDBACK",
DBUS_WB_TYPE="B3_REGISTERED_FEEDBACK",
)
defaults.update(kwargs)
parameters = {"p_{}".format(k): v for k, v in defaults.items()}

i_adr_o = Signal(32)
d_adr_o = Signal(32)
self.specials += Instance("mor1kx",
p_FEATURE_INSTRUCTIONCACHE="ENABLED",
p_OPTION_ICACHE_BLOCK_WIDTH=4,
p_OPTION_ICACHE_SET_WIDTH=8,
p_OPTION_ICACHE_WAYS=1,
p_OPTION_ICACHE_LIMIT_WIDTH=31,
p_FEATURE_DATACACHE="ENABLED",
p_OPTION_DCACHE_BLOCK_WIDTH=4,
p_OPTION_DCACHE_SET_WIDTH=8,
p_OPTION_DCACHE_WAYS=1,
p_OPTION_DCACHE_LIMIT_WIDTH=31,
p_FEATURE_TIMER="NONE",
p_OPTION_PIC_TRIGGER="LEVEL",
p_FEATURE_SYSCALL="NONE",
p_FEATURE_TRAP="NONE",
p_FEATURE_RANGE="NONE",
p_FEATURE_OVERFLOW="NONE",
p_FEATURE_ADDC="ENABLED",
p_FEATURE_CMOV="ENABLED",
p_FEATURE_FFL1="ENABLED",
p_OPTION_CPU0="CAPPUCCINO",
p_OPTION_RESET_PC=reset_pc,
p_IBUS_WB_TYPE="B3_REGISTERED_FEEDBACK",
p_DBUS_WB_TYPE="B3_REGISTERED_FEEDBACK",

i_clk=ClockSignal(),
i_rst=ResetSignal(),

@@ -69,7 +72,9 @@ def __init__(self, platform, reset_pc):
i_dwbm_dat_i=d.dat_r,
i_dwbm_ack_i=d.ack,
i_dwbm_err_i=d.err,
i_dwbm_rty_i=0)
i_dwbm_rty_i=0,

**parameters)

self.comb += [
self.ibus.adr.eq(i_adr_o[2:]),
3 changes: 2 additions & 1 deletion misoc/integration/soc_core.py
Original file line number Diff line number Diff line change
@@ -71,7 +71,8 @@ def __init__(self, platform, clk_freq,
if cpu_type == "lm32":
self.submodules.cpu = lm32.LM32(platform, self.cpu_reset_address)
elif cpu_type == "or1k":
self.submodules.cpu = mor1kx.MOR1KX(platform, self.cpu_reset_address)
self.submodules.cpu = mor1kx.MOR1KX(platform,
OPTION_RESET_PC=self.cpu_reset_address)
else:
raise ValueError("Unsupported CPU type: {}".format(cpu_type))
self.submodules.tmpu = tmpu.TMPU(self.cpu.dbus)