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base repository: azonenberg/yosys
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base: 203b521a781c
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head repository: azonenberg/yosys
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compare: 6fed2dc996a5
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- 10 commits
- 11 files changed
- 3 contributors
Commits on Feb 12, 2017
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Commits on Feb 13, 2017
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More progress on Firrtl backend.
Chisel -> Firrtl -> Verilog -> Firrtl -> Verilog is successful for a simple rocket-chip design.
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Commits on Feb 14, 2017
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Merge pull request YosysHQ#313 from azidar/bugfix-assign-wmask
More progress on Firrtl backend.
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