@@ -109,7 +109,7 @@ class MiniSoC(BaseSoC):
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}
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mem_map .update (BaseSoC .mem_map )
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- def __init__ (self , * args , ** kwargs ):
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+ def __init__ (self , * args , ethmac_nrxslots = 2 , ethmac_ntxslots = 2 , ** kwargs ):
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BaseSoC .__init__ (self , * args , ** kwargs )
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self .csr_devices += ["ethphy" , "ethmac" ]
@@ -118,7 +118,8 @@ def __init__(self, *args, **kwargs):
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eth_clocks = self .platform .request ("eth_clocks" )
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self .submodules .ethphy = LiteEthPHY (eth_clocks ,
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self .platform .request ("eth" ), clk_freq = self .clk_freq )
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- self .submodules .ethmac = LiteEthMAC (phy = self .ethphy , dw = 32 , interface = "wishbone" )
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+ self .submodules .ethmac = LiteEthMAC (phy = self .ethphy , dw = 32 , interface = "wishbone" ,
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+ nrxslots = ethmac_nrxslots , ntxslots = ethmac_ntxslots )
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self .add_wb_slave (mem_decoder (self .mem_map ["ethmac" ]), self .ethmac .bus )
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self .add_memory_region ("ethmac" , self .mem_map ["ethmac" ] | self .shadow_base , 0x2000 )
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