targets/atlys_edid_debug: add comments

timvideos · Oct 13, 2015 · 80a6b7c · 80a6b7c
1 parent 658511b
commit 80a6b7c
Showing 1 changed file with 11 additions and 0 deletions.
diff --git a/targets/atlys_edid_debug.py b/targets/atlys_edid_debug.py
@@ -8,11 +8,22 @@
 from litescope.core.port import LiteScopeTerm
 from litescope.frontend.logic_analyzer import LiteScopeLogicAnalyzer
 
+
 class UARTVirtualPhy:
     def __init__(self):
         self.sink = Sink([("data", 8)])
         self.source = Source([("data", 8)])
 
+# This SoC was used to debug EDID transactions between video sources and the board.
+# To use it:
+#  - build this SoC & load it
+#  - wait for HDMI2USB prompt
+#  - change state of SW0
+#  - go to test/edid_debug
+#  - do make.py --port <your_uart_port> test_regs and verify you are able to get sysid/revision/frequency
+#  - do make.py --port <your_uart_port> test_la
+#  - connect your video source, this will trigger litescope capture and upload data.
+#  - you now have a .vcd you can analyze in GTKwave or others vcd viewers!
 
 class EDIDDebugSoC(VideomixerSoC):
     csr_map = {