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Manual update
filipswit authored Mar 1, 2018
1 parent 504bca7 commit 3d12a61
Showing 39 changed files with 51,476 additions and 45,917 deletions.
343 changes: 175 additions & 168 deletions ARTIQ_EE/PCB_Sayma_AMC/Manual/SaymaAMC.tex
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\input{tex/panel.tex}
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\input{tex/usb-uart.tex}
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\input{tex/power.tex}
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\input{tex/mmc.tex}
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\input{tex/wiki_introduction.tex}
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\input{tex/wiki_utca.tex}
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\input{tex/wiki_sayma.tex}
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%\input{tex/intro.tex}
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%\input{tex/description.tex}
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\input{tex/view.tex}
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\input{tex/routing.tex}
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\input{tex/clocking.tex}
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\input{tex/panel.tex}
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\input{tex/fmc.tex}
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\input{tex/usb-uart.tex}
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\input{tex/jtag.tex}
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%\input{tex/fpga.tex}
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\input{tex/power.tex}
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\input{tex/mmc.tex}
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\input{tex/housekeeping.tex}
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\input{tex/signals.tex}
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\input{tex/testing.tex}
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\begin{appendix}

\input{tex/appendix.tex}
\clearpage

\input{tex/gateware.tex}
\clearpage

\end{appendix}

\end{document}
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2,334 changes: 1,167 additions & 1,167 deletions ARTIQ_EE/PCB_Sayma_AMC/Manual/tex/appendix.tex

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24 changes: 14 additions & 10 deletions ARTIQ_EE/PCB_Sayma_AMC/Manual/tex/clocking.tex
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\section{Clocking}

This section describes how and where clock signals are routed.

\begin{figure}[htbp!]
\centering
\includegraphics[scale=0.2]{img/clk.eps}\\
\caption{Clocks} \label{clocking}
\end{figure}

\section{Clocking}

This section describes how and where clock signals are routed.

\begin{figure}[htbp!]
\centering
\includegraphics[scale=0.2]{img/clk.eps}\\
\caption{Clocks} \label{clocking}
\end{figure}
\begin{itemize}
\item OSC2 - 50MHz main clock source for FPGA resources
\item OSC3 - place-holder
\item OSC4 dedicated 200MHz clock source to gigabit transceivers
\end{itemize}
184 changes: 92 additions & 92 deletions ARTIQ_EE/PCB_Sayma_AMC/Manual/tex/description.tex
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@@ -1,92 +1,92 @@
%\section{Project description}
%
%The Sayma AMC is a Advanced Mezzanine Card carrier board to carry FMC cards and connect RTM modules.
%
%

\section{Functional specifications}

\noindent

\textbf{Programmable resources:}

\begin{itemize}
\item Xilinx Kintex UltraScale – XCKU040-1FFVA-1156C FPGA
\begin{itemize}
\item speed grade: -1
\item 20 GTH transceivers (Max Preformance 16.3 Gb/s)
\end{itemize}
\item MMC: LPC17762984
\end{itemize}

\textbf{Memory:}

\begin{itemize}
\item 512Mb DDR3 SDRAM (32-bit interface), 800MHz (clock)
\item 1Gb DDR3 SDRAM (64-bit interface), 800MHz (clock)
\item SPI Flash for FPGA configuration. Accessible by MMC
\item SPI Flash for user data storage
\item EEPROM with MAC and unique ID

\end{itemize}

\textbf{Connectivity:}

\begin{itemize}
\item 1 high pin count (HPC) FMC slot for single width mezzanine card
\item Micro-USB UART connected to FPGA or MMC
\item Stand-alone 12V power connector
\item MGT (Multi-Gigabit Transceiver) connected to:
\begin{itemize}
% \item FMC x1
\item RTM x16
\item Fat\_Pipe1 x2
% \item AMC P2P x4
% \item Port 0 – possibility connected to SATA
\item SFP x2
\end{itemize}
% \item RTM connector with 8 GTP routed to it. Compatible with Sayma RTM module.
\item Port 0 – possibility connected to SATA
\item RTM connector compatible with Sayma RTM module

\end{itemize}

\textbf{Supply:}

\begin{itemize}
\item Monitoring of voltage and Power supply for RTM 12V and FMC 12V
\item FMC VADJ fixed to 1V8
\item Monitoring current of all FMC buses
\item Stand-alone power connectore
% \item Czy Exar monitoruje powera?

\end{itemize}


\textbf{Clocking:}

\begin{itemize}
\item Clock recovery Si5324
\item UFL CLK input
\item SMA CLK output


\end{itemize}


\textbf{Other:}

\begin{itemize}
\item Temperature, voltage and current monitoring for critical power buses
\item Temperature monitoring: FMC1, supply, FPGA core, DDR memory
\item JTAG multiplexer (SCANSTA) for FMC access, local JTAG port and remote debug/Chipscope via Ethernet

\end{itemize}








%\section{Project description}
%
%The Sayma AMC is a Advanced Mezzanine Card carrier board to carry FMC cards and connect RTM modules.
%
%

\section{Functional specifications}

\noindent

\textbf{Programmable resources:}

\begin{itemize}
\item Xilinx Kintex UltraScale – XCKU040-1FFVA-1156C FPGA
\begin{itemize}
\item speed grade: -1
\item 20 GTH transceivers (Max Preformance 16.3 Gb/s)
\end{itemize}
\item MMC: LPC17762984
\end{itemize}

\textbf{Memory:}

\begin{itemize}
\item 512Mb DDR3 SDRAM (32-bit interface), 800MHz (clock)
\item 1Gb DDR3 SDRAM (64-bit interface), 800MHz (clock)
\item SPI Flash for FPGA configuration. Accessible by MMC
\item SPI Flash for user data storage
\item EEPROM with MAC and unique ID

\end{itemize}

\textbf{Connectivity:}

\begin{itemize}
\item 1 high pin count (HPC) FMC slot for single width mezzanine card
\item Micro-USB UART connected to FPGA or MMC
\item Stand-alone 12V power connector
\item MGT (Multi-Gigabit Transceiver) connected to:
\begin{itemize}
% \item FMC x1
\item RTM x16
\item Fat\_Pipe1 x2
% \item AMC P2P x4
% \item Port 0 – possibility connected to SATA
\item SFP x2
\end{itemize}
% \item RTM connector with 8 GTP routed to it. Compatible with Sayma RTM module.
\item Port 0 – possibility connected to SATA
\item RTM connector compatible with Sayma RTM module

\end{itemize}

\textbf{Supply:}

\begin{itemize}
\item Monitoring of voltage and Power supply for RTM 12V and FMC 12V
\item FMC VADJ fixed to 1V8
\item Monitoring current of all FMC buses
\item Stand-alone power connectore
% \item Czy Exar monitoruje powera?

\end{itemize}


\textbf{Clocking:}

\begin{itemize}
\item Clock recovery Si5324
\item UFL CLK input
\item SMA CLK output


\end{itemize}


\textbf{Other:}

\begin{itemize}
\item Temperature, voltage and current monitoring for critical power buses
\item Temperature monitoring: FMC1, supply, FPGA core, DDR memory
\item JTAG multiplexer (SCANSTA) for FMC access, local JTAG port and remote debug/Chipscope via Ethernet

\end{itemize}








202 changes: 101 additions & 101 deletions ARTIQ_EE/PCB_Sayma_AMC/Manual/tex/fmc.tex
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@@ -1,102 +1,102 @@
\section{FMC}



\begin{itemize}
\item VADJ: 1V8 @ 1A
\item FPGA Banks: 47HP and 48HP
\end{itemize}


The connector is compliant with ANSI/VITA 57.1 FMC-LPC Standard.\\

%---------------------------------------------------------FMC1
\begin{footnotesize}
\begin{longtable}{|p{7cm}|p{1cm}|p{5cm}|}
\hline
\multicolumn{3}{|c|}{\multirow{2}{*}{\textbf{\large{FMC1}}}}\\
\multicolumn{3}{|c|}{} \\ \hline
FPGA signal & FPGA ball & Signal on the board \\ \hline
IO\_L12P\_T1U\_N10\_GC\_47 & AA24 & FMC1\_CLK0\_M2C\_P \\ \hline
IO\_L12N\_T1U\_N11\_GC\_47 & AA25 & FMC1\_CLK0\_M2C\_N \\ \hline
IO\_L11P\_T1U\_N8\_GC\_47 & Y23 & FMC1\_CLK1\_M2C\_P \\ \hline
IO\_L11N\_T1U\_N9\_GC\_47 & AA23 & FMC1\_CLK1\_M2C\_N \\ \hline
IO\_L12P\_T1U\_N10\_GC\_48 & AC31 & FMC1\_GBTCLK0\_M2C\_P \\ \hline
IO\_L12N\_T1U\_N11\_GC\_48 & AC32 & FMC1\_GBTCLK0\_M2C\_N \\ \hline
IO\_L1P\_T0L\_N0\_DBC\_48 & AE27 & FMC1\_DP0\_M2C\_P \\ \hline
IO\_L1N\_T0L\_N1\_DBC\_48 & AF27 & FMC1\_DP0\_M2C\_N \\ \hline
IO\_L2P\_T0L\_N2\_48 & AE28 & FMC1\_DP0\_C2M\_P \\ \hline
IO\_L2N\_T0L\_N3\_48 & AF28 & FMC1\_DP0\_C2M\_N \\ \hline
IO\_L13P\_T2L\_N0\_GC\_QBC\_48 & AA32 & FMC1\_LA00\_CC\_P \\ \hline
IO\_L13N\_T2L\_N1\_GC\_QBC\_48 & AB32 & FMC1\_LA00\_CC\_N \\ \hline
IO\_L14P\_T2L\_N2\_GC\_48 & AB30 & FMC1\_LA01\_CC\_P \\ \hline
IO\_L14N\_T2L\_N3\_GC\_48 & AB31 & FMC1\_LA01\_CC\_N \\ \hline
IO\_L8P\_T1L\_N2\_AD5P\_48 & AF33 & FMC1\_LA02\_P \\ \hline
IO\_L8N\_T1L\_N3\_AD5N\_48 & AG34 & FMC1\_LA02\_N \\ \hline
IO\_L21P\_T3L\_N4\_AD8P\_48 & V33 & FMC1\_LA03\_P \\ \hline
IO\_L21N\_T3L\_N5\_AD8N\_48 & W34 & FMC1\_LA03\_N \\ \hline
IO\_L7P\_T1L\_N0\_QBC\_AD13P\_48 & AG31 & FMC1\_LA04\_P \\ \hline
IO\_L7N\_T1L\_N1\_QBC\_AD13N\_48 & AG32 & FMC1\_LA04\_N \\ \hline
IO\_L10P\_T1U\_N6\_QBC\_AD4P\_48 & AE33 & FMC1\_LA05\_P \\ \hline
IO\_L10N\_T1U\_N7\_QBC\_AD4N\_48 & AF34 & FMC1\_LA05\_N \\ \hline
IO\_L15P\_T2L\_N4\_AD11P\_48 & AC34 & FMC1\_LA06\_P \\ \hline
IO\_L15N\_T2L\_N5\_AD11N\_48 & AD34 & FMC1\_LA06\_N \\ \hline
IO\_L18P\_T2U\_N10\_AD2P\_48 & AC33 & FMC1\_LA07\_P \\ \hline
IO\_L18N\_T2U\_N11\_AD2N\_48 & AD33 & FMC1\_LA07\_N \\ \hline
IO\_L11P\_T1U\_N8\_GC\_48 & AD30 & FMC1\_LA08\_P \\ \hline
IO\_L11N\_T1U\_N9\_GC\_48 & AD31 & FMC1\_LA08\_N \\ \hline
IO\_L9P\_T1L\_N4\_AD12P\_48 & AE32 & FMC1\_LA09\_P \\ \hline
IO\_L9N\_T1L\_N5\_AD12N\_48 & AF32 & FMC1\_LA09\_N \\ \hline
IO\_L17P\_T2U\_N8\_AD10P\_48 & AA34 & FMC1\_LA10\_P \\ \hline
IO\_L17N\_T2U\_N9\_AD10N\_48 & AB34 & FMC1\_LA10\_N \\ \hline
IO\_L16P\_T2U\_N6\_QBC\_AD3P\_48 & AA29 & FMC1\_LA11\_P \\ \hline
IO\_L16N\_T2U\_N7\_QBC\_AD3N\_48 & AB29 & FMC1\_LA11\_N \\ \hline
IO\_L24P\_T3U\_N10\_48 & V31 & FMC1\_LA12\_P \\ \hline
IO\_L24N\_T3U\_N11\_48 & W31 & FMC1\_LA12\_N \\ \hline
IO\_L19P\_T3L\_N0\_DBC\_AD9P\_48 & W33 & FMC1\_LA13\_P \\ \hline
IO\_L19N\_T3L\_N1\_DBC\_AD9N\_48 & Y33 & FMC1\_LA13\_N \\ \hline
IO\_L23P\_T3U\_N8\_48 & U34 & FMC1\_LA14\_P \\ \hline
IO\_L23N\_T3U\_N9\_48 & V34 & FMC1\_LA14\_N \\ \hline
IO\_L22P\_T3U\_N6\_DBC\_AD0P\_48 & Y31 & FMC1\_LA15\_P \\ \hline
IO\_L22N\_T3U\_N7\_DBC\_AD0N\_48 & Y32 & FMC1\_LA15\_N \\ \hline
IO\_L20P\_T3L\_N2\_AD1P\_48 & W30 & FMC1\_LA16\_P \\ \hline
IO\_L20N\_T3L\_N3\_AD1N\_48 & Y30 & FMC1\_LA16\_N \\ \hline
IO\_L13P\_T2L\_N0\_GC\_QBC\_47 & W23 & FMC1\_LA17\_CC\_P \\ \hline
IO\_L13N\_T2L\_N1\_GC\_QBC\_47 & W24 & FMC1\_LA17\_CC\_N \\ \hline
IO\_L14P\_T2L\_N2\_GC\_47 & W25 & FMC1\_LA18\_CC\_P \\ \hline
IO\_L14N\_T2L\_N3\_GC\_47 & Y25 & FMC1\_LA18\_CC\_N \\ \hline
IO\_L16P\_T2U\_N6\_QBC\_AD3P\_47 & V22 & FMC1\_LA19\_P \\ \hline
IO\_L16N\_T2U\_N7\_QBC\_AD3N\_47 & V23 & FMC1\_LA19\_N \\ \hline
IO\_L17P\_T2U\_N8\_AD10P\_47 & T22 & FMC1\_LA20\_P \\ \hline
IO\_L17N\_T2U\_N9\_AD10N\_47 & T23 & FMC1\_LA20\_N \\ \hline
IO\_L18P\_T2U\_N10\_AD2P\_47 & V21 & FMC1\_LA21\_P \\ \hline
IO\_L18N\_T2U\_N11\_AD2N\_47 & W21 & FMC1\_LA21\_N \\ \hline
IO\_L15P\_T2L\_N4\_AD11P\_47 & U21 & FMC1\_LA22\_P \\ \hline
IO\_L15N\_T2L\_N5\_AD11N\_47 & U22 & FMC1\_LA22\_N \\ \hline
IO\_L10P\_T1U\_N6\_QBC\_AD4P\_47 & AB21 & FMC1\_LA23\_P \\ \hline
IO\_L10N\_T1U\_N7\_QBC\_AD4N\_47 & AC21 & FMC1\_LA23\_N \\ \hline
IO\_L8P\_T1L\_N2\_AD5P\_47 & AC22 & FMC1\_LA24\_P \\ \hline
IO\_L8N\_T1L\_N3\_AD5N\_47 & AC23 & FMC1\_LA24\_N \\ \hline
IO\_L9P\_T1L\_N4\_AD12P\_47 & AA20 & FMC1\_LA25\_P \\ \hline
IO\_L9N\_T1L\_N5\_AD12N\_47 & AB20 & FMC1\_LA25\_N \\ \hline
IO\_L7P\_T1L\_N0\_QBC\_AD13P\_47 & AA22 & FMC1\_LA26\_P \\ \hline
IO\_L7N\_T1L\_N1\_QBC\_AD13N\_47 & AB22 & FMC1\_LA26\_N \\ \hline
IO\_L6P\_T0U\_N10\_AD6P\_47 & AB25 & FMC1\_LA27\_P \\ \hline
IO\_L6N\_T0U\_N11\_AD6N\_47 & AB26 & FMC1\_LA27\_N \\ \hline
IO\_L24P\_T3U\_N10\_47 & V26 & FMC1\_LA28\_P \\ \hline
IO\_L24N\_T3U\_N11\_47 & W26 & FMC1\_LA28\_N \\ \hline
IO\_L23P\_T3U\_N8\_47 & V29 & FMC1\_LA29\_P \\ \hline
IO\_L23N\_T3U\_N9\_47 & W29 & FMC1\_LA29\_N \\ \hline
IO\_L22P\_T3U\_N6\_DBC\_AD0P\_47 & U26 & FMC1\_LA30\_P \\ \hline
IO\_L22N\_T3U\_N7\_DBC\_AD0N\_47 & U27 & FMC1\_LA30\_N \\ \hline
IO\_L21P\_T3L\_N4\_AD8P\_47 & W28 & FMC1\_LA31\_P \\ \hline
IO\_L21N\_T3L\_N5\_AD8N\_47 & Y28 & FMC1\_LA31\_N \\ \hline
IO\_L20P\_T3L\_N2\_AD1P\_47 & U24 & FMC1\_LA32\_P \\ \hline
IO\_L20N\_T3L\_N3\_AD1N\_47 & U25 & FMC1\_LA32\_N \\ \hline
IO\_L19P\_T3L\_N0\_DBC\_AD9P\_47 & V27 & FMC1\_LA33\_P \\ \hline
IO\_L19N\_T3L\_N1\_DBC\_AD9N\_47 & V28 & FMC1\_LA33\_N \\ \hline
VREF\_48 & AA30 & FMC1\_VREF\_A\_M2C \\ \hline
VREF\_47 & V24 & FMC1\_VREF\_A\_M2C \\ \hline

\end{longtable}
\section{FMC}



\begin{itemize}
\item VADJ: 1V8 @ 1A
\item FPGA Banks: 47HP and 48HP
\end{itemize}


The connector is compliant with ANSI/VITA 57.1 FMC-LPC Standard.\\

%---------------------------------------------------------FMC1
\begin{footnotesize}
\begin{longtable}{|p{7cm}|p{1cm}|p{5cm}|}
\hline
\multicolumn{3}{|c|}{\multirow{2}{*}{\textbf{\large{FMC1}}}}\\
\multicolumn{3}{|c|}{} \\ \hline
FPGA signal & FPGA ball & Signal on the board \\ \hline
IO\_L12P\_T1U\_N10\_GC\_47 & AA24 & FMC1\_CLK0\_M2C\_P \\ \hline
IO\_L12N\_T1U\_N11\_GC\_47 & AA25 & FMC1\_CLK0\_M2C\_N \\ \hline
IO\_L11P\_T1U\_N8\_GC\_47 & Y23 & FMC1\_CLK1\_M2C\_P \\ \hline
IO\_L11N\_T1U\_N9\_GC\_47 & AA23 & FMC1\_CLK1\_M2C\_N \\ \hline
IO\_L12P\_T1U\_N10\_GC\_48 & AC31 & FMC1\_GBTCLK0\_M2C\_P \\ \hline
IO\_L12N\_T1U\_N11\_GC\_48 & AC32 & FMC1\_GBTCLK0\_M2C\_N \\ \hline
IO\_L1P\_T0L\_N0\_DBC\_48 & AE27 & FMC1\_DP0\_M2C\_P \\ \hline
IO\_L1N\_T0L\_N1\_DBC\_48 & AF27 & FMC1\_DP0\_M2C\_N \\ \hline
IO\_L2P\_T0L\_N2\_48 & AE28 & FMC1\_DP0\_C2M\_P \\ \hline
IO\_L2N\_T0L\_N3\_48 & AF28 & FMC1\_DP0\_C2M\_N \\ \hline
IO\_L13P\_T2L\_N0\_GC\_QBC\_48 & AA32 & FMC1\_LA00\_CC\_P \\ \hline
IO\_L13N\_T2L\_N1\_GC\_QBC\_48 & AB32 & FMC1\_LA00\_CC\_N \\ \hline
IO\_L14P\_T2L\_N2\_GC\_48 & AB30 & FMC1\_LA01\_CC\_P \\ \hline
IO\_L14N\_T2L\_N3\_GC\_48 & AB31 & FMC1\_LA01\_CC\_N \\ \hline
IO\_L8P\_T1L\_N2\_AD5P\_48 & AF33 & FMC1\_LA02\_P \\ \hline
IO\_L8N\_T1L\_N3\_AD5N\_48 & AG34 & FMC1\_LA02\_N \\ \hline
IO\_L21P\_T3L\_N4\_AD8P\_48 & V33 & FMC1\_LA03\_P \\ \hline
IO\_L21N\_T3L\_N5\_AD8N\_48 & W34 & FMC1\_LA03\_N \\ \hline
IO\_L7P\_T1L\_N0\_QBC\_AD13P\_48 & AG31 & FMC1\_LA04\_P \\ \hline
IO\_L7N\_T1L\_N1\_QBC\_AD13N\_48 & AG32 & FMC1\_LA04\_N \\ \hline
IO\_L10P\_T1U\_N6\_QBC\_AD4P\_48 & AE33 & FMC1\_LA05\_P \\ \hline
IO\_L10N\_T1U\_N7\_QBC\_AD4N\_48 & AF34 & FMC1\_LA05\_N \\ \hline
IO\_L15P\_T2L\_N4\_AD11P\_48 & AC34 & FMC1\_LA06\_P \\ \hline
IO\_L15N\_T2L\_N5\_AD11N\_48 & AD34 & FMC1\_LA06\_N \\ \hline
IO\_L18P\_T2U\_N10\_AD2P\_48 & AC33 & FMC1\_LA07\_P \\ \hline
IO\_L18N\_T2U\_N11\_AD2N\_48 & AD33 & FMC1\_LA07\_N \\ \hline
IO\_L11P\_T1U\_N8\_GC\_48 & AD30 & FMC1\_LA08\_P \\ \hline
IO\_L11N\_T1U\_N9\_GC\_48 & AD31 & FMC1\_LA08\_N \\ \hline
IO\_L9P\_T1L\_N4\_AD12P\_48 & AE32 & FMC1\_LA09\_P \\ \hline
IO\_L9N\_T1L\_N5\_AD12N\_48 & AF32 & FMC1\_LA09\_N \\ \hline
IO\_L17P\_T2U\_N8\_AD10P\_48 & AA34 & FMC1\_LA10\_P \\ \hline
IO\_L17N\_T2U\_N9\_AD10N\_48 & AB34 & FMC1\_LA10\_N \\ \hline
IO\_L16P\_T2U\_N6\_QBC\_AD3P\_48 & AA29 & FMC1\_LA11\_P \\ \hline
IO\_L16N\_T2U\_N7\_QBC\_AD3N\_48 & AB29 & FMC1\_LA11\_N \\ \hline
IO\_L24P\_T3U\_N10\_48 & V31 & FMC1\_LA12\_P \\ \hline
IO\_L24N\_T3U\_N11\_48 & W31 & FMC1\_LA12\_N \\ \hline
IO\_L19P\_T3L\_N0\_DBC\_AD9P\_48 & W33 & FMC1\_LA13\_P \\ \hline
IO\_L19N\_T3L\_N1\_DBC\_AD9N\_48 & Y33 & FMC1\_LA13\_N \\ \hline
IO\_L23P\_T3U\_N8\_48 & U34 & FMC1\_LA14\_P \\ \hline
IO\_L23N\_T3U\_N9\_48 & V34 & FMC1\_LA14\_N \\ \hline
IO\_L22P\_T3U\_N6\_DBC\_AD0P\_48 & Y31 & FMC1\_LA15\_P \\ \hline
IO\_L22N\_T3U\_N7\_DBC\_AD0N\_48 & Y32 & FMC1\_LA15\_N \\ \hline
IO\_L20P\_T3L\_N2\_AD1P\_48 & W30 & FMC1\_LA16\_P \\ \hline
IO\_L20N\_T3L\_N3\_AD1N\_48 & Y30 & FMC1\_LA16\_N \\ \hline
IO\_L13P\_T2L\_N0\_GC\_QBC\_47 & W23 & FMC1\_LA17\_CC\_P \\ \hline
IO\_L13N\_T2L\_N1\_GC\_QBC\_47 & W24 & FMC1\_LA17\_CC\_N \\ \hline
IO\_L14P\_T2L\_N2\_GC\_47 & W25 & FMC1\_LA18\_CC\_P \\ \hline
IO\_L14N\_T2L\_N3\_GC\_47 & Y25 & FMC1\_LA18\_CC\_N \\ \hline
IO\_L16P\_T2U\_N6\_QBC\_AD3P\_47 & V22 & FMC1\_LA19\_P \\ \hline
IO\_L16N\_T2U\_N7\_QBC\_AD3N\_47 & V23 & FMC1\_LA19\_N \\ \hline
IO\_L17P\_T2U\_N8\_AD10P\_47 & T22 & FMC1\_LA20\_P \\ \hline
IO\_L17N\_T2U\_N9\_AD10N\_47 & T23 & FMC1\_LA20\_N \\ \hline
IO\_L18P\_T2U\_N10\_AD2P\_47 & V21 & FMC1\_LA21\_P \\ \hline
IO\_L18N\_T2U\_N11\_AD2N\_47 & W21 & FMC1\_LA21\_N \\ \hline
IO\_L15P\_T2L\_N4\_AD11P\_47 & U21 & FMC1\_LA22\_P \\ \hline
IO\_L15N\_T2L\_N5\_AD11N\_47 & U22 & FMC1\_LA22\_N \\ \hline
IO\_L10P\_T1U\_N6\_QBC\_AD4P\_47 & AB21 & FMC1\_LA23\_P \\ \hline
IO\_L10N\_T1U\_N7\_QBC\_AD4N\_47 & AC21 & FMC1\_LA23\_N \\ \hline
IO\_L8P\_T1L\_N2\_AD5P\_47 & AC22 & FMC1\_LA24\_P \\ \hline
IO\_L8N\_T1L\_N3\_AD5N\_47 & AC23 & FMC1\_LA24\_N \\ \hline
IO\_L9P\_T1L\_N4\_AD12P\_47 & AA20 & FMC1\_LA25\_P \\ \hline
IO\_L9N\_T1L\_N5\_AD12N\_47 & AB20 & FMC1\_LA25\_N \\ \hline
IO\_L7P\_T1L\_N0\_QBC\_AD13P\_47 & AA22 & FMC1\_LA26\_P \\ \hline
IO\_L7N\_T1L\_N1\_QBC\_AD13N\_47 & AB22 & FMC1\_LA26\_N \\ \hline
IO\_L6P\_T0U\_N10\_AD6P\_47 & AB25 & FMC1\_LA27\_P \\ \hline
IO\_L6N\_T0U\_N11\_AD6N\_47 & AB26 & FMC1\_LA27\_N \\ \hline
IO\_L24P\_T3U\_N10\_47 & V26 & FMC1\_LA28\_P \\ \hline
IO\_L24N\_T3U\_N11\_47 & W26 & FMC1\_LA28\_N \\ \hline
IO\_L23P\_T3U\_N8\_47 & V29 & FMC1\_LA29\_P \\ \hline
IO\_L23N\_T3U\_N9\_47 & W29 & FMC1\_LA29\_N \\ \hline
IO\_L22P\_T3U\_N6\_DBC\_AD0P\_47 & U26 & FMC1\_LA30\_P \\ \hline
IO\_L22N\_T3U\_N7\_DBC\_AD0N\_47 & U27 & FMC1\_LA30\_N \\ \hline
IO\_L21P\_T3L\_N4\_AD8P\_47 & W28 & FMC1\_LA31\_P \\ \hline
IO\_L21N\_T3L\_N5\_AD8N\_47 & Y28 & FMC1\_LA31\_N \\ \hline
IO\_L20P\_T3L\_N2\_AD1P\_47 & U24 & FMC1\_LA32\_P \\ \hline
IO\_L20N\_T3L\_N3\_AD1N\_47 & U25 & FMC1\_LA32\_N \\ \hline
IO\_L19P\_T3L\_N0\_DBC\_AD9P\_47 & V27 & FMC1\_LA33\_P \\ \hline
IO\_L19N\_T3L\_N1\_DBC\_AD9N\_47 & V28 & FMC1\_LA33\_N \\ \hline
VREF\_48 & AA30 & FMC1\_VREF\_A\_M2C \\ \hline
VREF\_47 & V24 & FMC1\_VREF\_A\_M2C \\ \hline

\end{longtable}
\end{footnotesize}
24 changes: 12 additions & 12 deletions ARTIQ_EE/PCB_Sayma_AMC/Manual/tex/fpga.tex
Original file line number Diff line number Diff line change
@@ -1,12 +1,12 @@
\section{FPGA bootstrapping}


\noindent
\textbf{Xilinx User Guide:} \href{https://www.xilinx.com/support/documentation/user_guides/ug570-ultrascale-configuration.pdf}{https://www.xilinx.com/support/documentation/user\_guides/ug570-ultrascale-configuration.pdf}\\

To load FPGA .bit into flash Vivado in version minimum 16.4 is needed.\\
\textbf{Vivado WebPack:}\href{https://www.xilinx.com/support/download.html}{https://www.xilinx.com/support/download.html}

Alternatively Vivado Lab tools (previously Lab Tools) can be used.\\
\textbf{Vivado Lab Edition:}\href{https://www.xilinx.com/support/download.html}{https://www.xilinx.com/support/download.html}

\section{FPGA bootstrapping}


\noindent
\textbf{Xilinx User Guide:} \href{https://www.xilinx.com/support/documentation/user_guides/ug570-ultrascale-configuration.pdf}{https://www.xilinx.com/support/documentation/user\_guides/ug570-ultrascale-configuration.pdf}\\

To load FPGA .bit into flash Vivado in version minimum 16.4 is needed.\\
\textbf{Vivado WebPack:}\href{https://www.xilinx.com/support/download.html}{https://www.xilinx.com/support/download.html}

Alternatively Vivado Lab tools (previously Lab Tools) can be used.\\
\textbf{Vivado Lab Edition:}\href{https://www.xilinx.com/support/download.html}{https://www.xilinx.com/support/download.html}

546 changes: 546 additions & 0 deletions ARTIQ_EE/PCB_Sayma_AMC/Manual/tex/gateware.tex

Large diffs are not rendered by default.

34 changes: 34 additions & 0 deletions ARTIQ_EE/PCB_Sayma_AMC/Manual/tex/glossary.tex
Original file line number Diff line number Diff line change
@@ -0,0 +1,34 @@
\section{Glossary}

\begin{description}
\item[AFE] Analogue front-end.
\item[AMC Module or Modul] An AMC Module is a mezzanine or modular add-on card that extends the
functionality of a Carrier Board. The term is also used to generically refer to the
different varieties of Multi-Width and Multi-Height Modules.
\item[BaseMod] Base-band input/output mezzanine.
\item[COTS] Commercial off-the-shelf. Product which is designed and can be easily purchased.
\item[EEM] Eurocard Extension Module is a Sinara standard for low-cost, low-bandwidth peripherals that are controlled by ARTIQ DRTIO.
\item[Fat Pipes] Ports 4 though 11 of the AMC Connector constitute the Fat Pipes Region. This
Region of Ports is intended for the assignment of multiple Lane interfaces, also
called “fat pipes”. Fat Pipe 1 [Ports 4-7], Fat Pipe [Ports 8-11].
\item[FMC] FPGA Mezzanine Card
\item[HEPP] High Energy Physics. ???
\item[Hot Swap] To remove a component (e.g., an AMC Module) from a system (e.g., an AMC Carrier
AdvancedTCA Board) and plug in a new one while the power is still on and the
system is still operating.
\item[IPMB] ntelligent Platform Management Bus. The lowest level hardware management bus
as described in the Intelligent Platform Management Bus Communications Protocol
Specification.
\item[Management Power or MP] The 3.3V power for a Module's Management function, individually provided to each Slot by the Carrier
\item[MGT] Multi-Gigabit Transceiver.
\item[MixMod] An up-converting mezzanine, using an analogue IQ mixer to mix the input and output RF signals with a LO supplied by Sayma.
\item[MMC] Module Management Controller. The MMC is the required intelligent controller that
manages the Module and is interfaced to the Carrier via IPMB-Local.
\item[RFBP] RF Backplane.
\item[RTM] Rear Transition Module.
\item[Sayma] Smart Arbitrary Waveform Generator, providing 8 channels of 1.2 GSPS 16-bit DACs (2.4 GHz DAC clock) and 125 MSPS 16-bit ADCs. It consists of an AMC, providing the high-speed digital logic, and a RTM, holding the data converters and analog components.
\item[Sianra] Open-source hardware ecosystem originally designed for use in quantum physics experiments running the ARTIQ control software. It is licensed under CERN OHL v1.2.
\item[uTCA] Micro Telecommunications Computing Architecture. MicroTCA is a modular, open standard for building high performance computer systems in a small form factor.
\end{description}


36 changes: 18 additions & 18 deletions ARTIQ_EE/PCB_Sayma_AMC/Manual/tex/hist.tex
Original file line number Diff line number Diff line change
@@ -1,18 +1,18 @@



\begin{table}[h!]
\vspace{5cm}
\centering
\begin{center}
\begin{tabular}{|l|l|}
\hline
\textbf{\rule[-2ex]{0pt}{5.5ex} Document version:} & Preliminary \\ \hline
\textbf{\rule[-2ex]{0pt}{5.5ex} Issue Date:} & \today \\ \hline
\textbf{\rule[-2ex]{0pt}{5.5ex} Written by:} & Filip Świtakowski \\ \hline
\textbf{\rule[-2ex]{0pt}{5.5ex} Approved by:} & Greg Kasprowicz \\ \hline
\textbf{\rule[-2ex]{0pt}{5.5ex} Document title:} & \nazwa - specification \\ \hline

\end{tabular}
\end{center}
\end{table}



\begin{table}[h!]
\vspace{5cm}
\centering
\begin{center}
\begin{tabular}{|l|l|}
\hline
\textbf{\rule[-2ex]{0pt}{5.5ex} Document version:} & Preliminary \\ \hline
\textbf{\rule[-2ex]{0pt}{5.5ex} Issue Date:} & \today \\ \hline
\textbf{\rule[-2ex]{0pt}{5.5ex} Written by:} & Filip Świtakowski \\ \hline
\textbf{\rule[-2ex]{0pt}{5.5ex} Approved by:} & Greg Kasprowicz \\ \hline
\textbf{\rule[-2ex]{0pt}{5.5ex} Document title:} & \nazwa - specification \\ \hline

\end{tabular}
\end{center}
\end{table}
81 changes: 42 additions & 39 deletions ARTIQ_EE/PCB_Sayma_AMC/Manual/tex/housekeeping.tex
Original file line number Diff line number Diff line change
@@ -1,39 +1,42 @@
\section{Housekeeping Signals}
\subsection{sensors}
Temperature:\\
%\begin{itemize}
% \item IC8 (0x4B) -NOR Flash
% \item IC34 (0x49) -FPGA
% \item IC35 (0x4A)-under SFPs
% \item IC36 (0x4F)-power section
% \item IC37 (0x24) -middle od the board
%\end{itemize}
\begin{longtable}{|c|c|c|c|c|}\hline
No & Addr. & placement & Type & Accuracy \\ \hline
IC8 & 0x4B & NOR Flash & LM75 & +/- 2 \\ \hline
IC34 & 0x49 & FPGA & LM75 & +/- 2 \\ \hline
IC35 & 0x4A & Under SFPs & LM75 & +/- 2 \\ \hline
IC36 & 0x4F & power section & LM75 & +/- 2 \\ \hline
IC37 & 0x24 & middle of the board & MAX664A & +/- 1 \\ \hline
\end{longtable}

All temperature sensors are tied tohether to one I2C bus - I2C\_SENS. \\


Current:
%\begin{itemize}
% \item IC27 (0x40)-RTM\_P12V0
% \item IC28 (0x41)-FMC\_P12V0
%\end{itemize}
\begin{longtable}{|c|c|c|c|c|}\hline
No & Addr. & placement & Type & Accuracy \\ \hline
IC27 & 0x40 &RTM\_P12V0& INA219 & +/- 0.2\% \\ \hline
IC28 & 0x41 &FMC\_P12V0& INA219 & +/- 0.2\% \\ \hline
\end{longtable}


All current sensors are tied tohether to one I2C bus - PM\_I2C. \\

\subsection{Safety interlocks}

\todo[inline]{TBD OVERTEMPn}
\section{Housekeeping Signals}
Both MMC and FPGA can acces to any of I2C buses as is in Figure \ref{I2C}. MMC collects all data from all sensors connected to I2C bus. Then the data can be transfered via IPMI to MCH. For now MCH get only information about AMC and RTM to allow power supply.

\subsection{sensors}
Temperature:\\
%\begin{itemize}
% \item IC8 (0x4B) -NOR Flash
% \item IC34 (0x49) -FPGA
% \item IC35 (0x4A)-under SFPs
% \item IC36 (0x4F)-power section
% \item IC37 (0x24) -middle od the board
%\end{itemize}
\begin{longtable}{|c|c|c|c|c|}\hline
No & Addr. & placement & Type & Accuracy \\ \hline
IC8 & 0x4B & NOR Flash & LM75 & +/- 2 \\ \hline
IC34 & 0x49 & FPGA & LM75 & +/- 2 \\ \hline
IC35 & 0x4A & Under SFPs & LM75 & +/- 2 \\ \hline
IC36 & 0x4F & power section & LM75 & +/- 2 \\ \hline
IC37 & 0x24 & middle of the board & MAX664A & +/- 1 \\ \hline
\end{longtable}

All temperature sensors are tied tohether to one I2C bus - SENS\_I2C. \\


Current:
%\begin{itemize}
% \item IC27 (0x40)-RTM\_P12V0
% \item IC28 (0x41)-FMC\_P12V0
%\end{itemize}
\begin{longtable}{|c|c|c|c|c|}\hline
No & Addr. & placement & Type & Accuracy \\ \hline
IC27 & 0x40 &RTM\_P12V0& INA219 & +/- 0.2\% \\ \hline
IC28 & 0x41 &FMC\_P12V0& INA219 & +/- 0.2\% \\ \hline
\end{longtable}


All current sensors are tied tohether to one I2C bus - PM\_I2C. \\

\subsection{Safety interlocks}


Temperature interlock is available on RTM board only and gets activated after reaching 80 degrees. This is hardware interlock and cannot be deactivated. Dedicated LED (LD15) gets on and RTM power supply is off until the temperature is exceeded
98 changes: 49 additions & 49 deletions ARTIQ_EE/PCB_Sayma_AMC/Manual/tex/intro.tex
Original file line number Diff line number Diff line change
@@ -1,49 +1,49 @@
%\section{Introduction to Micro TCA}




%The MTCA platform is available on the market for over
%ten years. It evolved from telecommunication ATCA standard. The MTCA sandard utilizes ATCA-defined AMC boards
%used directly in dedicated chassis. It also defines MTCA
%Carrier Hub (MCH) which controlls multiple slave boards, known as Advanced Mezzanine Cards (AMCs) via a high-speed digital backplane. AMC card can be equipped with FPGA Mzzanine Cards (FMCs) which are I/O modules pluggable to High-pin Count (HPC) or Low-pin Count (LPC) connector.
%
%%which consists of Ethernet hub and crate
%%management system.
%The MTCA crates are available in several
%form-factors for industrial, aviation and military use.
%User can easily extend and adopt the standard to particular application by selection of
%proper chassis, cooling method, computing and connectivity
%technology while keeping same mechanical, electrical standard and software architecture.\\


%MicroTCA (uTCA) is Sinara's preferred form-factor for hardware with high-speed data converters requiring deterministic phase control, such as the Sayma 2.4GSPS smart arbitrary waveform generator (SAWG).
%
%uTCA is a modular, open standard originally developed by the telecommunications industry. It allows a single rack master -- the Micro TCA Carrier Hub (MCH) -- to control multiple slave boards, known as Advanced Mezzanine Cards (AMCs) via a high-speed digital backplane. uTCA chassis and backplanes are available commercially of the shelf (COTS).
%%
%We make use of the most recent extension to the uTCA standard, uTCA.4. Originating in the high-energy and particle physics (HEPP) community, uTCA.4 introduces rear-transition modules (RTMs) along with a second backplane for low-noise RF signals (RFBP). Each RTM connects to an AMC (one RTM per AMC). Typically, the AMCs hold FPGAs and other high-speed digital hardware, communicating with the MCH via gigabit serial links over the AMC backplane. The RTMs hold data converters and other low-noise analog components, controlled by the corresponding AMC. The RFBP provides low-noise clocks and local oscillators (LOs). The RTMs and RFBP are screened from the AMCs to minimise interference from the high-speed digital logic

\section{Glossary}

\begin{description}
\item[AMC Module or Modul] An AMC Module is a mezzanine or modular add-on card that extends the
functionality of a Carrier Board. The term is also used to generically refer to the
different varieties of Multi-Width and Multi-Height Modules.
\item[Fat Pipes] Ports 4 though 11 of the AMC Connector constitute the Fat Pipes Region. This
Region of Ports is intended for the assignment of multiple Lane interfaces, also
called “fat pipes”. Fat Pipe 1 [Ports 4-7], Fat Pipe [Ports 8-11].
\item[FMC] FPGA Mezzanine Card
\item[Hot Swap] To remove a component (e.g., an AMC Module) from a system (e.g., an AMC Carrier
AdvancedTCA Board) and plug in a new one while the power is still on and the
system is still operating.
\item[Management Power or MP] The 3.3V power for a Module's Management function, individually provided to each Slot by the Carrier
\item[IPMB] ntelligent Platform Management Bus. The lowest level hardware management bus
as described in the Intelligent Platform Management Bus Communications Protocol
Specification.
\item[MGT] Multi-Gigabit Transceiver
\item[MMC] Module Management Controller. The MMC is the required intelligent controller that
manages the Module and is interfaced to the Carrier via IPMB-Local
\item[RTM] Rear Transition Module
\end{description}


%\section{Introduction to Micro TCA}




%The MTCA platform is available on the market for over
%ten years. It evolved from telecommunication ATCA standard. The MTCA sandard utilizes ATCA-defined AMC boards
%used directly in dedicated chassis. It also defines MTCA
%Carrier Hub (MCH) which controlls multiple slave boards, known as Advanced Mezzanine Cards (AMCs) via a high-speed digital backplane. AMC card can be equipped with FPGA Mzzanine Cards (FMCs) which are I/O modules pluggable to High-pin Count (HPC) or Low-pin Count (LPC) connector.
%
%%which consists of Ethernet hub and crate
%%management system.
%The MTCA crates are available in several
%form-factors for industrial, aviation and military use.
%User can easily extend and adopt the standard to particular application by selection of
%proper chassis, cooling method, computing and connectivity
%technology while keeping same mechanical, electrical standard and software architecture.\\


%MicroTCA (uTCA) is Sinara's preferred form-factor for hardware with high-speed data converters requiring deterministic phase control, such as the Sayma 2.4GSPS smart arbitrary waveform generator (SAWG).
%
%uTCA is a modular, open standard originally developed by the telecommunications industry. It allows a single rack master -- the Micro TCA Carrier Hub (MCH) -- to control multiple slave boards, known as Advanced Mezzanine Cards (AMCs) via a high-speed digital backplane. uTCA chassis and backplanes are available commercially of the shelf (COTS).
%%
%We make use of the most recent extension to the uTCA standard, uTCA.4. Originating in the high-energy and particle physics (HEPP) community, uTCA.4 introduces rear-transition modules (RTMs) along with a second backplane for low-noise RF signals (RFBP). Each RTM connects to an AMC (one RTM per AMC). Typically, the AMCs hold FPGAs and other high-speed digital hardware, communicating with the MCH via gigabit serial links over the AMC backplane. The RTMs hold data converters and other low-noise analog components, controlled by the corresponding AMC. The RFBP provides low-noise clocks and local oscillators (LOs). The RTMs and RFBP are screened from the AMCs to minimise interference from the high-speed digital logic

\section{Glossary}

\begin{description}
\item[AMC Module or Modul] An AMC Module is a mezzanine or modular add-on card that extends the
functionality of a Carrier Board. The term is also used to generically refer to the
different varieties of Multi-Width and Multi-Height Modules.
\item[Fat Pipes] Ports 4 though 11 of the AMC Connector constitute the Fat Pipes Region. This
Region of Ports is intended for the assignment of multiple Lane interfaces, also
called “fat pipes”. Fat Pipe 1 [Ports 4-7], Fat Pipe [Ports 8-11].
\item[FMC] FPGA Mezzanine Card
\item[Hot Swap] To remove a component (e.g., an AMC Module) from a system (e.g., an AMC Carrier
AdvancedTCA Board) and plug in a new one while the power is still on and the
system is still operating.
\item[Management Power or MP] The 3.3V power for a Module's Management function, individually provided to each Slot by the Carrier
\item[IPMB] ntelligent Platform Management Bus. The lowest level hardware management bus
as described in the Intelligent Platform Management Bus Communications Protocol
Specification.
\item[MGT] Multi-Gigabit Transceiver
\item[MMC] Module Management Controller. The MMC is the required intelligent controller that
manages the Module and is interfaced to the Carrier via IPMB-Local
\item[RTM] Rear Transition Module
\end{description}


65 changes: 34 additions & 31 deletions ARTIQ_EE/PCB_Sayma_AMC/Manual/tex/jtag.tex
Original file line number Diff line number Diff line change
@@ -1,31 +1,34 @@
\section{JTAG}

JTAG can be connected either from USB (FT4232H) or from IDC header. IDC header is permanenty connected to Scansta. \\
The USB-UART bridge can be enabled by setting high on ADBUS7.\\



\begin{figure}[htbp!]
\centering
\includegraphics[scale=0.5]{img/jtag.png}\\
\caption{USB-->JTAG}
\end{figure}
General block scheme of Scansta connections is shown below.\\

\begin{figure}[htbp!]
\centering
\includegraphics[scale=0.4]{img/scansta.eps}\\
\caption{SCANSTA bloch scheme}
\end{figure}

\textit{\textbf{Note:} The FMC2 and PS is not used.}\\

Scansta112 is 7-Port Multidrop JTAG Multiplexer. It is used to partition scan chains into managable sizes, or to isolate specific devices onto a separate chain. By default Scansta input signal is from IDC header. AMC JTAG is connected to Master Port on SCANSTA, so it can be used as Master or Slave module. The rest modules (MMC, FPGA, FMC, RTM) are tied to slave SCANSTA outputs. \\
Simplified instruction if using SCANSTA can be found under: \href{http://www.ti.com/lit/an/snla068c/snla068c.pdf}{http://www.ti.com/lit/an/snla068c/snla068c.pdf}
In Sayma AMC, SCANSTA112 is used in Transparent Sticher Mode. In this mode, the IC can be configured via hardware to skip the addressing protocol needed, sothere is no need to run a SVF configuration file on IMPACT when programming the FPGA bitstream.

\begin{figure}[htbp!]
\centering
\includegraphics[scale=0.4]{img/jtagchain.eps}\\
\caption{SCANSTA JTAG chain}
\end{figure}
\section{JTAG}
Scansta112 is 7-Port Multidrop JTAG Multiplexer. It is used to partition scan chains into managable sizes, or to isolate specific devices onto a separate chain. By default Scansta input signal is from IDC header. AMC JTAG is connected to Master Port on SCANSTA, so it can be used as Master or Slave module. The rest modules (MMC, FPGA, FMC, RTM) are tied to slave SCANSTA outputs. \\

Tere are two JTAG sources – either AMC connector ( JSM module) or USB to JTAG bridge (FTDI chip). There is also onboard JTAG connector (Xilinx type) -J3. Insertion of JTAG programmer probe deactivates the FTDI JTAG connectivity and forces SCANSTA chip set this port as master port. By default SCANSTA selects AMC port as master one.\\


In Sayma AMC, SCANSTA112 is used in Transparent Sticher Mode. In this mode, the IC can be configured via hardware to skip the addressing protocol needed, sothere is no need to run a SVF configuration file on IMPACT when programming the FPGA bitstream.\\
\begin{figure}[htbp!]
\centering
\includegraphics[scale=0.5]{img/jtag.png}\\
\caption{USB-->JTAG}
\end{figure}
\clearpage
General block scheme of Scansta connections is shown below.\\

\begin{figure}[htbp!]
\centering
\includegraphics[scale=0.4]{img/scansta.eps}\\
\caption{SCANSTA bloch scheme}
\end{figure}

\textit{\textbf{Note:} The FMC2 and PS is not used.}\\


Each of JTAG slave devices is connected directly to SCANSTA. SCANSTA allows to connect all devices in chain witn an option to pass one or more devices, intention in Figure \ref{jtagchain}.

\begin{figure}[htbp!]
\centering
\includegraphics[scale=0.4]{img/jtagchain.eps}\\
\caption{SCANSTA JTAG chain} \label{jtagchain}
\end{figure}


Simplified instruction if using SCANSTA can be found under: \href{http://www.ti.com/lit/an/snla068c/snla068c.pdf}{http://www.ti.com/lit/an/snla068c/snla068c.pdf}
164 changes: 94 additions & 70 deletions ARTIQ_EE/PCB_Sayma_AMC/Manual/tex/mmc.tex
Original file line number Diff line number Diff line change
@@ -1,70 +1,94 @@
\section{MMC}

\subsection{MMC steps during booting}

\begin{itemize}

\item configures CPU, UART
\item sets port directions
\item enables VCCINT PSU
\item enables P5V0 PSU (helper PSU)
\item enables Exar PSU. It boots from its own EEPROM
\item waits 200ms
\item configures SCANSTA chip in stitcher mode. If RTM is inserted, it enables its JTAG port
\item configures I2C switch base address
\item initializes default RTM power state to off
\item initializes Ethernet PHY chip in RGMII mode using pin strap.
\item waits 200ms
\item initializes I2C controller and chain (switch)
\item configures Si5324
\item checks if RTM is inserted, if yes, then enables its power, waits 200ms and initializes RTM power supply via I2C. It also configures Si5324 on RTM
\item runs task.\\

The task performs following functions:

\item blinks front panel LEDs alternately
\item checks if FPGA is configured. If not, it keeps Ethernet PHY in reset state. Once FPGA gets configured, it initializes the PHY.
\item checks if RTM is unplugged. If not, it switches the power off to make sure it is off during hotplug.
\end{itemize}

\subsection{Bootstraping}

The MMC can be upgraded by USB cable and NXP programmer(can be used other programmer but make sure that header shorts pins 3, 5, 9) using \href{http://www.flashmagictool.com/}{Flashmagic} or any other software which can talk with NXP bootloader. The source code is written in C and can be found on github.\\
\textbf{Source code:} \href{https://github.com/m-labs/sinara/tree/master/SAYMA\_firmware}{https://github.com/m-labs/sinara/tree/master/SAYMA\_firmware}.\\
\textbf{pre-compiled binary:} \href{https://github.com/m-labs/mmc-firmware/releases}{https://github.com/m-labs/mmc-firmware/releases}\\

To compile binaries \href{https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/lpc-cortex-m-mcus/lpc1100-cortex-m0-plus-m0/lpcxpresso-ide-v8.2.2:LPCXPRESSO?tab=Design_Tools_Tab}{LPCXpresso} is needed.

\subsection{Functionality}

\todo[inline]{needed?}

\subsection{Exar debugging}

In case of chip failure, i.g.overvoltage, overcurrent, etc., there is possibility to check chip status via UART. In this case in UART console, Exar register readout can be done by typing 'P' character.\\

\begin{figure}[htbp!]
\centering
\includegraphics[scale=0.6]{img/exarreg.png}\\
\caption{Exar register }
\end{figure}
\clearpage
\subsection{PHY debugging}

In case of chip failure, there is possibility to check chip status via UART. In this case in UART console, Ethernet PHY content can be read by typing 'E' character

\begin{figure}[htbp!]
\centering
\includegraphics[scale=0.6]{img/phyreg.png}\\
\caption{Ethernet PHY register }
\end{figure}

\subsection{RGMII Ethernet }

\todo[inline]{TBD. Not sure what should it contain.}

\subsection{OpenMMC}

\textbf{OpenMMC Project:}\href{https://github.com/lnls-dig/openMMC}{https://github.com/lnls-dig/openMMC}

\todo[inline]{TBD}
\section{MMC}

\subsection{MMC steps during booting}

\begin{itemize}

\item configures CPU, UART from own FLASH
\item sets IO port directions
\item enables VCCINT PSU
\item enables P5V0 PSU (helper PSU)
\item enables Exar PSU. It boots from its own EEPROM
\item waits 200ms
\item configures SCANSTA chip in stitcher mode. If RTM is inserted, it enables its JTAG port
\item configures I2C switch base address for master ports - MMC, FPGA
\item initializes default RTM power state to off
\item initializes Ethernet PHY chip in RGMII mode using pin strap.
\item waits 200ms
\item initializes I2C controller and chain (switch)
\item configures Si5324
\item checks if RTM is inserted, if yes, then enables its power, waits 200ms and initializes RTM power supply via RTM\_I2C. It also configures Si5324 on RTM
\item runs task.\\

The task performs following functions:

\item checks if FPGA is configured. If not, it keeps Ethernet PHY in reset state. Once FPGA gets configured, it initializes the PHY.
\item checks if RTM is unplugged. If not, it switches the power off to make sure it is off during hotplug.
\end{itemize}
\textit{\textbf{Note:}Configuration CPU, UART does not affect with any changes of LED indicators.}


\subsection{Bootstraping}
To compile binaries \href{https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/lpc-cortex-m-mcus/lpc1100-cortex-m0-plus-m0/lpcxpresso-ide-v8.2.2:LPCXPRESSO?tab=Design_Tools_Tab}{LPCXpresso} in newest version is needed.\\
\href{https://www.nxp.com/docs/en/user-guide/LPCXpresso_IDE_User_Guide.pdf}{LPCXpresso User Guide}

Another option is to compile under Linux using cmake toolchain in version 4.9.3.
\begin{lstlisting}
cmake & arm-none-eabi-gcc
\end{lstlisting}

\begin{itemize}
\item Header flashing

The MMC can be upgraded by USB cable and NXP programmer(can be used other programmer but make sure that header shorts pins 3, 5, 9) using \href{http://www.flashmagictool.com/}{Flashmagic} or any other software which can talk with NXP bootloader. The tested programmer is LPCLink V2. Flashing using programmer allows to debug.

\item USB flashing
The MMC can be upgraded using USB and flashmagic software. This option only allows to flash IC, without any debug option.
Steps to flash using USB:
\begin{itemize}
\item Set serial console 115200 8n1
\item Press front-panel button -PB3 to trigger MMD to dump to serial console
\item Set LPC1776, 8MHz oscillator, select hex file and press start
\end{itemize}

\end{itemize}

The source code is written in C and can be found on github.\\
\textbf{Source code:} \href{https://github.com/m-labs/sinara/tree/master/SAYMA\_firmware}{https://github.com/m-labs/sinara/tree/master/SAYMA\_firmware}.\\
\textbf{pre-compiled binary:} \href{https://github.com/m-labs/mmc-firmware/releases}{https://github.com/m-labs/mmc-firmware/releases}\\



%\subsection{Functionality}
%
%\todo[inline]{needed?}

\subsection{Exar debugging}

In case of chip failure, i.g.overvoltage, overcurrent, etc., there is possibility to check chip status via UART. In this case in UART console, Exar register readout can be done by typing 'P' character.\\

\begin{figure}[htbp!]
\centering
\includegraphics[scale=0.6]{img/exarreg.png}\\
\caption{Exar register }
\end{figure}
\clearpage
\subsection{PHY debugging}

In case of chip failure, there is possibility to check chip status via UART. In this case in UART console, Ethernet PHY content can be read by typing 'E' character

\begin{figure}[htbp!]
\centering
\includegraphics[scale=0.6]{img/phyreg.png}\\
\caption{Ethernet PHY register }
\end{figure}

\subsection{Ethernet }

There is no Ethernet sharing between MMC and FPGA due to speed difference between RGMII and RMII. PHY does not provide link speed translation.

\subsection{OpenMMC}

\textbf{OpenMMC Project:}\href{https://github.com/lnls-dig/openMMC}{https://github.com/lnls-dig/openMMC}

\todo[inline]{TBD}
416 changes: 243 additions & 173 deletions ARTIQ_EE/PCB_Sayma_AMC/Manual/tex/panel.tex

Large diffs are not rendered by default.

231 changes: 129 additions & 102 deletions ARTIQ_EE/PCB_Sayma_AMC/Manual/tex/power.tex
Original file line number Diff line number Diff line change
@@ -1,102 +1,129 @@
\section{Power}
\subsection{Power supply}

\todo[inline]{TBD voltage noise}
The 12V power can be connected either from AMC connector or from Stand alone power supply connected to Molex Connector(39-28-1043).

\begin{figure}[htbp!]
\centering
\includegraphics[scale=0.2]{img/molex.jpg}\\
\caption{Power connector}
\end{figure}
\begin{center}
\begin{tabular}{|c|c|} \hline
{\LARGE GND} & {\LARGE GND} \\ \hline
{\LARGE +12} & {\LARGE +12} \\ \hline
\end{tabular}
\end{center}

Maximum board(AMC+RTM module) power consumption estimate to 3A @ 12V.\\

\textit{\textbf{Note:} Please note that power consumption mostly depends from FPGA configuration. \\}

\begin{itemize}


\item Input voltage range: 10.8-13.2 [V]\\
\item The board needs active cooling. Approx. 20CFM in 20 C air.\\

\end{itemize}
\subsection{Power configuration}

\subsubsection{Power map}


\begin{figure}[htbp!]
\centering
\includegraphics[scale=0.3]{img/pwr.eps}\\
\caption{Power map}
\end{figure}
\clearpage

\begin{longtable}{|c|c|c|} \hline
\multicolumn{3}{|c|}{voltages and currents} \\ \hline
P0V9 & 0.9V & 10A \\ \hline
P0V95 & 0.95V & 31mA\\ \hline
P1V0 & 1.0V & 3A\\ \hline
P1V2 & 1.2V & 0.6A\\ \hline
P1V5 & 1.5V & 7.5A\\ \hline
P1V8 & 1.8V & 1.6A\\ \hline
P3V3 & 3.3 V & 2A\\ \hline
P3V3MP & 3.3V & 0.18A \\ \hline
P5V0 & 5.0V & 0.5A\\ \hline
\end{longtable}

\begin{longtable}{|c|c|c|} \hline
\multicolumn{3}{|c|}{Maximum RTM voltages and currents} \\ \hline
P12V0 & 12V & 3A \\ \hline
P3V3MP\_RTM & 3.3V & 30mA \\ \hline
\end{longtable}

\subsubsection{Exar parameters}

Exar chip has 4 configurable outputs with configirable current limits. Channels 1, 3, 4 are power un on chip enable with 10ms delay. Channel 2 is power on 'EN\_PSU\_CH' signal. \\
%3V3 LDO is power on independently. \\

\begin{figure}[htbp!]
\centering
\includegraphics[scale=0.6]{img/exar1.png}\\
\caption{Exar configuration}
\end{figure}

\begin{figure}[htbp!]
\centering
\includegraphics[scale=0.6]{img/exar2.png}\\
\caption{Exar power on delays}
\end{figure}

\clearpage


\subsubsection{Exar configuration}
Exar chips are configured via I2C bus (MUX Port 5) or directly by connecting to W1 (call-out 28) header. For proper configuration \textbf{Exar Power Architect} in version \textbf{5.2-r1} is needed.
% Configuration files can be found at github in folder \href{https://github.com/m-labs/sinara/tree/master/EXAR\_config}{m-labs/sinara/Exar\_config}\\

\noindent
\textbf{Exar Power Archtect 5.2-r1:}
\href{https://www.exar.com/content/document.ashx?id=21632}{https://www.exar.com/content/document.ashx?id=21632}\\
\textbf{Configuration files:}
\href{https://github.com/m-labs/sinara/tree/master/EXAR\_config}{https://github.com/m-labs/sinara/tree/master/EXAR\_config}\\
\textbf{Datasheet:}\href{https://www.exar.com/ds/xr77129_1a_120514.pdf}{https://www.exar.com/ds/xr77129\_1a\_120514.pdf}\\
\textbf{Quick Start Guide:} \href{https://www.exar.com/files/powerxr/PA5-QSG_110_010614.pdf}{https://www.exar.com/files/powerxr/PA5-QSG\_110\_010614.pdf}\\


Actual voltages and current consumption, temperature can be found in Chip Dashboard. There is also oportunity to adjust settings.

\begin{figure}[htbp!]
\centering
\includegraphics[scale=0.6]{img/exarprog.png}\\
\caption{Chip Dashboard}
\end{figure}


\section{Power}
\subsection{Power supply}
The card can operate as stand alone devide, or plugged into a uTCA crate. While working standalone the power is provided by Molex Connector(39-28-1043) -J4. The pinout is shown in Figure \ref{power}.\\
When the card is inserted to the crate the power is applied from AMC connector -J2, +12V (8 power lines) and +3.3\_MP(1 line).
At the begening +3.3\_MP power up the MMC, then +12 is converted to lower voltages, simplified power map is in figure \ref{powermap}. All on board voltages (exept P3V3\_MP) are enabled by MMC. There are two types of power distributors, fixed LDOs and Exar chip - quad channel digital Pulse Width Modulated (PWM) step down (buck) controller. Exar allows for adjust power parameters and for set particular power oorder. Exar firmware monitors current and responds if its too high. Additionaly all LDOs have connected PowerGood outputs so it is possible to read the proper state of all power busses.
\todo[inline]{TBD Can MMC readout Exar debug information?}
\todo[inline]{TBD voltage noise}

\begin{figure}[htbp!]
\centering
\includegraphics[scale=0.2]{img/molex.jpg}\\
\caption{Power connector} \label{power}
\end{figure}
\begin{center}
\begin{tabular}{|c|c|} \hline
{\LARGE GND} & {\LARGE GND} \\ \hline
{\LARGE +12} & {\LARGE +12} \\ \hline
\end{tabular}
\end{center}

Maximum board(AMC+RTM module) power consumption estimate to 3A @ 12V.\\

\textit{\textbf{Note:} Please note that power consumption mostly depends from FPGA configuration. \\}

\begin{itemize}


\item Input voltage range: 10.8-13.2 [V]\\
\item The board needs active cooling. Approx. 20CFM in 20 C air.\\

\end{itemize}

Exar chips are configured via PM\_I2C bus (I2CMUX5) or directly by connecting to W1 (call-out 28) header. For proper configuration \textbf{Exar Power Architect} in version \textbf{5.2-r1} is needed.
% Configuration files can be found at github in folder \href{https://github.com/m-labs/sinara/tree/master/EXAR\_config}{m-labs/sinara/Exar\_config}\\

\noindent
\textbf{Exar Power Archtect 5.2-r1:}
\href{https://www.exar.com/content/document.ashx?id=21632}{https://www.exar.com/content/document.ashx?id=21632}\\
\textbf{Configuration files:}
\href{https://github.com/m-labs/sinara/tree/master/EXAR\_config}{https://github.com/m-labs/sinara/tree/master/EXAR\_config}\\
\textbf{Datasheet:}\href{https://www.exar.com/ds/xr77129_1a_120514.pdf}{https://www.exar.com/ds/xr77129\_1a\_120514.pdf}\\
\textbf{Quick Start Guide:} \href{https://www.exar.com/files/powerxr/PA5-QSG_110_010614.pdf}{https://www.exar.com/files/powerxr/PA5-QSG\_110\_010614.pdf}\\


Actual voltages and current consumption, temperature can be found in Chip Dashboard. There is also oportunity to adjust settings.

\begin{figure}[htbp!]
\centering
\includegraphics[scale=0.6]{img/exarprog.png}\\
\caption{Chip Dashboard}
\end{figure}


\subsection{Power configuration}

\subsubsection{Power map}


\begin{figure}[htbp!]
\centering
\includegraphics[scale=0.3]{img/pwr.eps}\\
\caption{Power map} \label{powermap}
\end{figure}
\clearpage

\begin{longtable}{|c|c|c|} \hline
\multicolumn{3}{|c|}{voltages and currents} \\ \hline
P0V9 & 0.9V & 10A \\ \hline
P0V95 & 0.95V & 31mA\\ \hline
P1V0 & 1.0V & 3A\\ \hline
P1V2 & 1.2V & 0.6A\\ \hline
P1V5 & 1.5V & 7.5A\\ \hline
P1V8 & 1.8V & 1.6A\\ \hline
P3V3 & 3.3 V & 2A\\ \hline
P3V3MP & 3.3V & 0.18A \\ \hline
P5V0 & 5.0V & 0.5A\\ \hline
\end{longtable}

\begin{longtable}{|c|c|c|} \hline
\multicolumn{3}{|c|}{Maximum RTM voltages and currents} \\ \hline
P12V0 & 12V & 3A \\ \hline
P3V3MP\_RTM & 3.3V & 30mA \\ \hline
\end{longtable}

\subsubsection{Exar parameters}

Exar chip(XR77129) has 4 configurable outputs with configirable current limits. Each channel can be confugured individually. It is possible to set voltage, current limit and power sequencing. In Figure \ref{exar1} we can see that main power supply is 12V, Under Voltage Lockout(UVLO) is set to 6V, so below this value chip will shutdown all channels. When the temperature rise under Over Temperature Protection (OTP) 105 degrees, the chip will generate warning event and restart. \\
All 4 channells can be grouped together and will start-up and shut-down in an user defined sequwnce. Selecting none means channels will not be assigned to any group and therefore, will be controlled independently. Group 0 is controlled by ENABLE or PM\_I2C command. Group 1 can be controlled by GPIO or by PM\_I2C command. By selecting 'Wait PGOOD' next channel will not power up untill current channel reaches the target level. Delay is an additional delay time which postpone after power up one and another channel in group.\\
In on-going Exar configuration - Figure \ref{exar2}, power sequencing looks like this: After Enable from MMC P1V0 start-up, after it reaches proper value, Exar waits 10ms and turn ramp up another channel in this group - P1V8. In the same order is ramp up last channel in this group. Finally on command 'EN\_PSU\_CH' P3V3 ramp up.



\begin{figure}[htbp!]
\centering
\includegraphics[scale=0.5]{img/exar1.png}\\
\caption{Exar configuration} \label{exar1}
\end{figure}

\begin{figure}[htbp!]
\centering
\includegraphics[scale=0.5]{img/exar2.png}\\
\caption{Exar power on delays} \label{exar2}
\end{figure}

\clearpage


%\subsubsection{Exar configuration}
%Exar chips are configured via I2C bus (MUX Port 5) or directly by connecting to W1 (call-out 28) header. For proper configuration \textbf{Exar Power Architect} in version \textbf{5.2-r1} is needed.
%% Configuration files can be found at github in folder \href{https://github.com/m-labs/sinara/tree/master/EXAR\_config}{m-labs/sinara/Exar\_config}\\
%
%\noindent
%\textbf{Exar Power Archtect 5.2-r1:}
%\href{https://www.exar.com/content/document.ashx?id=21632}{https://www.exar.com/content/document.ashx?id=21632}\\
%\textbf{Configuration files:}
%\href{https://github.com/m-labs/sinara/tree/master/EXAR\_config}{https://github.com/m-labs/sinara/tree/master/EXAR\_config}\\
%\textbf{Datasheet:}\href{https://www.exar.com/ds/xr77129_1a_120514.pdf}{https://www.exar.com/ds/xr77129\_1a\_120514.pdf}\\
%\textbf{Quick Start Guide:} \href{https://www.exar.com/files/powerxr/PA5-QSG_110_010614.pdf}{https://www.exar.com/files/powerxr/PA5-QSG\_110\_010614.pdf}\\
%
%
%Actual voltages and current consumption, temperature can be found in Chip Dashboard. There is also oportunity to adjust settings.
%
% \begin{figure}[htbp!]
% \centering
% \includegraphics[scale=0.6]{img/exarprog.png}\\
% \caption{Chip Dashboard}
% \end{figure}
%

97 changes: 73 additions & 24 deletions ARTIQ_EE/PCB_Sayma_AMC/Manual/tex/routing.tex
Original file line number Diff line number Diff line change
@@ -1,24 +1,73 @@
\section{Routing}


This section contain general bloch scheme of SAYMA AMC board and I2C map with addresses. General Block Scheme -figure \ref{BlockScheme}
shows more importand connections between components. I2C connections with addresses can be found in figure \ref{I2C}. Detailed clocking scheme can be found in next paragraph in figure \ref{clocking}.
\begin{figure}[htbp!]
\centering
\includegraphics[scale=0.2]{img/sch.eps}\\
\caption{General Block Scheme}\label{BlockScheme}
\end{figure}


\begin{figure}[htbp!]
\centering
\includegraphics[scale=0.2]{img/sch_mgt.eps}\\
\caption{MGT} \label{MGT}
\end{figure}

\begin{figure}[htbp!]
\centering
\includegraphics[scale=0.2]{img/i2c.eps}\\
\caption{I2C} \label{I2C}
\end{figure}

\section{Routing}


This section contain general blockm scheme of SAYMA AMC board and I2C map with addresses. General Block Scheme -figure \ref{BlockScheme}
shows more important connections between components. I2C connections with addresses can be found in figure \ref{I2C}. Detailed clocking scheme can be found in next paragraph in figure \ref{clocking}.
\begin{figure}[htbp!]
\centering
\includegraphics[scale=0.2]{img/sch.eps}\\
\caption{General Block Scheme}\label{BlockScheme}
\end{figure}

\clearpage5
\begin{figure}[htbp!]
\centering
\includegraphics[scale=0.2]{img/sch_mgt.eps}\\
\caption{MGT} \label{MGT}
\end{figure}

\begin{longtable}{|c|c|c|}\hline
Transceiver MGT & Direction & Routed to \\ \hline
0\_224 & TX & SFP1 \\ \hline
0\_224 & RX & SFP1 \\ \hline
1\_224 & TX & SFP2 \\ \hline
1\_224 & RX & SFP2 \\ \hline
2\_224 & TX & FP1 or MASTER SATA \\ \hline
2\_224 & RX & FP1 or MASTER SATA\\ \hline
3\_224 & TX & FP1 or SLAVE SATA\\ \hline
3\_224 & RX & FP1 or SLAVE SATA\\ \hline
0\_225 & TX & RTM\_GTP \\ \hline
0\_225 & RX & RTM\_GTP \\ \hline
1\_225 & TX & RTM\_GTP \\ \hline
1\_225 & RX & RTM\_GTP \\ \hline
2\_225 & TX & RTM\_GTP \\ \hline
2\_225 & RX & RTM\_GTP \\ \hline
3\_225 & TX & RTM\_GTP \\ \hline
3\_225 & RX & RTM\_GTP \\ \hline
0\_226 & TX & RTM\_GTP \\ \hline
0\_226 & RX & RTM\_GTP \\ \hline
1\_226 & TX & RTM\_GTP \\ \hline
1\_226 & RX & RTM\_GTP \\ \hline
2\_226 & TX & RTM\_GTP \\ \hline
2\_226 & RX & RTM\_GTP \\ \hline
3\_226 & TX & RTM\_GTP \\ \hline
3\_226 & RX & RTM\_GTP \\ \hline
0\_227 & TX & RTM\_GTP \\ \hline
0\_227 & RX & RTM\_GTP \\ \hline
1\_227 & TX & RTM\_GTP \\ \hline
1\_227 & RX & RTM\_GTP \\ \hline
2\_227 & TX & RTM\_GTP \\ \hline
2\_227 & RX & RTM\_GTP \\ \hline
3\_227 & TX & RTM\_GTP \\ \hline
4\_227 & RX & RTM\_GTP \\ \hline
0\_228 & TX & RTM\_GTP \\ \hline
0\_228 & RX & RTM\_GTP \\ \hline
1\_228 & TX & RTM\_GTP \\ \hline
1\_228 & RX & RTM\_GTP \\ \hline
2\_228 & TX & RTM\_GTP \\ \hline
2\_228 & RX & RTM\_GTP \\ \hline
3\_228 & TX & RTM\_GTP \\ \hline
4\_228 & RX & RTM\_GTP \\ \hline
\end{longtable}


\clearpage


The I2C MUX is made from two (TCA9548ARGER) I2C multiplexers. In Sayma AMC there are two main I2C busses: MMC\_I2C and FPGA\_I2C. Each of them is connected to one multiplexer. Outputs are tied together, so Masters (MMC and FPGA) can acces to any of 7 I2C busses. Addidtionaly MMC has acces to FPGA\_I2C and is connected to IPMB through AMC connector.\\
\begin{figure}[htbp!]
\centering
\includegraphics[scale=0.2]{img/i2c.eps}\\
\caption{I2C map with addresses in hex} \label{I2C}
\end{figure}

570 changes: 285 additions & 285 deletions ARTIQ_EE/PCB_Sayma_AMC/Manual/tex/signals.tex

Large diffs are not rendered by default.

4 changes: 2 additions & 2 deletions ARTIQ_EE/PCB_Sayma_AMC/Manual/tex/testing.tex
Original file line number Diff line number Diff line change
@@ -1,3 +1,3 @@
\section{Factory acceptance testing}

\section{Factory acceptance testing}

TBD
72 changes: 36 additions & 36 deletions ARTIQ_EE/PCB_Sayma_AMC/Manual/tex/title.tex
Original file line number Diff line number Diff line change
@@ -1,36 +1,36 @@
\begin{titlepage}




\textcolor{white}{xxx}
\vskip 1 true in

\begin{wrapfigure}{l}{0.01\textwidth}
\begin{center}
\vspace{-35pt}
\includegraphics[scale=0.5]{img/kropki.eps}
\end{center}
\end{wrapfigure}

\textbf{{\LARGE \nazwa}} \\
\linebreak
\textbf{ {\indent \indent \LARGE specification}}\\
\vskip 0.8 true in

\begin{figure}[htbp!]
\centering
\includegraphics[height=10cm]{img/SaymaT.jpg}\\
% \caption{v3.1(02.2017)}
\end{figure}
\begin{center}
v1.0(11.2017)
\end{center}

\vskip 0.7 true in





\end{titlepage}
\begin{titlepage}




\textcolor{white}{xxx}
\vskip 1 true in

\begin{wrapfigure}{l}{0.01\textwidth}
\begin{center}
\vspace{-35pt}
\includegraphics[scale=0.5]{img/kropki.eps}
\end{center}
\end{wrapfigure}

\textbf{{\LARGE \nazwa}} \\
\linebreak
\textbf{ {\indent \indent \LARGE specification}}\\
\vskip 0.8 true in

\begin{figure}[htbp!]
\centering
\includegraphics[height=10cm]{img/SaymaT.jpg}\\
% \caption{v3.1(02.2017)}
\end{figure}
\begin{center}
v1.0(11.2017)
\end{center}

\vskip 0.7 true in





\end{titlepage}
33 changes: 20 additions & 13 deletions ARTIQ_EE/PCB_Sayma_AMC/Manual/tex/usb-uart.tex
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@@ -1,13 +1,20 @@
\section{USB-UART}
\subsection{UART Switch}

UART from FPGA is connected through Multiplexer (SN74CB3T3257PW). Selection between MMC and USB is preformes automaticly. When micro-USB is connected S siglnal is high and Multiplexer connects USB to FPGA.\\

\subsection{USB-UART bridge}

The USB-UART bridge (FT4232H) requires USB device drivers, vailable free from http://www.ftdichip.com,
which are used to make the FT4232H on the Mini Module appear as a four virtual COM ports (VCP). This
then allows the user to communicate with the USB interface via a standard PC serial emulation port
(TTY).\\ Another FTDI USB driver, the D2XX driver, can also be used with application software to directly
access the FT4232H on the Mini Module though a DLL. \\

\section{USB-UART}
\subsection{USB console switch}

UART from FPGA is connected through Multiplexer (SN74CB3T3257PW). Selection between MMC and USB is preformed automaticly. When micro-USB is connected, +5V from USB bus switches the multiplexer to pass data from USB to FPGA, after un plugging cable, the switch signal S fall down and the multiplexer conects MMC to FPGA.\\

\begin{itemize}
\item PRI\_UART is connected to FPGA, configuration is 1N8 115200 baudrate
\item AUX\_UART is connected to FPGA, configuration is 1N8 115200 baudrate
\item UART1 is connected to MMC, configuration is 1N8 115200 baudrate
\item UART4 is connected to MMC, configuration is 1N8 115200 baudrate
\item MMC\_CONS\_PROG is conected to MMC, configuration is 1N8 115200 baudrate
\end{itemize}

\subsection{USB-UART bridge}

The USB-UART bridge (FT4232H) requires USB device drivers, vailable free from http://www.ftdichip.com,
which are used to make the FT4232H on the Mini Module appear as a four virtual COM ports (VCP). This
then allows the user to communicate with the USB interface via a standard PC serial emulation port
(TTY).\\

52 changes: 26 additions & 26 deletions ARTIQ_EE/PCB_Sayma_AMC/Manual/tex/view.tex
Original file line number Diff line number Diff line change
@@ -1,26 +1,26 @@

\section{Product view}

\begin{figure}[htbp!]
\centering
\includegraphics[height=10cm]{img/SaymaT.jpg}\\
\caption{Top view}
\end{figure}

\begin{figure}[htbp!]
\centering
\includegraphics[height=10cm]{img/SaymaB.jpg}\\
\caption{Bottom view}
\end{figure}

\begin{figure}[htbp!]
\centering
\includegraphics[width=14cm]{img/SaymaF.jpg}\\
\caption{Front view}
\end{figure}

\begin{figure}[htbp!]
\centering
\includegraphics[width=14cm]{img/back.jpg}\\
\caption{Back view}
\end{figure}

\section{Product view}

\begin{figure}[htbp!]
\centering
\includegraphics[height=10cm]{img/SaymaT.jpg}\\
\caption{Top view}
\end{figure}

\begin{figure}[htbp!]
\centering
\includegraphics[height=10cm]{img/SaymaB.jpg}\\
\caption{Bottom view}
\end{figure}

\begin{figure}[htbp!]
\centering
\includegraphics[width=14cm]{img/SaymaF.jpg}\\
\caption{Front view}
\end{figure}

\begin{figure}[htbp!]
\centering
\includegraphics[width=14cm]{img/back.jpg}\\
\caption{Back view}
\end{figure}
89 changes: 89 additions & 0 deletions ARTIQ_EE/PCB_Sayma_AMC/Manual/tex/wiki_introduction.tex
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@@ -0,0 +1,89 @@
\textbf {\Large Introduction to ARTIQ Sinara}\\

Sinara is an open-source hardware ecosystem originally designed for use
in quantum physics experiments running the
\href{https://m-labs.hk/artiq/}{ARTIQ} control software. It is licensed
under CERN OHL v1.2.

Control electronics used in many trapped-ion and other quantum physics
experiments suffers from a number of problems. In general, an ad-hoc
solution is hastily put together in-house without enough consideration
about good design, reproducibility, testing and documentation. This
makes those systems unreliable, fragile, and difficult to use and
maintain. It also duplicates work in different laboratories. In
addition, the performance and features of the existing systems
(e.g.~regarding pulse shaping abilities) is becoming insufficient for
some experiments.

To alleviate those problems, Sinara aims to be:

\begin{itemize}

\item
high-quality
\item
simple to use and ``turn-key''
\item
reproducible and open
\item
flexible and modular
\item
well tested
\item
well supported by the ARTIQ control software
\end{itemize}

%To see how Sinara can be used in your labs, take a look at our
%\href{CaseStudies}{case studies} showing Sinara in Action.

Sinara is currently developed by a \href{team}{collaboration} including
M-Labs, Warsaw University of Technology (WUT), US Army Research
Laboratory (ARL), the University of Oxford, the University of Maryland
and NIST. The majority of the hardware was designed by WUT. The work was
funded by ARL, Duke University, the University of Oxford, and the
University of Freiburg.\\

%\emph{Currently, much of this hardware is at the prototyping stage.}
%Information about the status of the various hardware projects making up
%Sinara can be found \href{Status}{here}. Advice about purchasing Sinara
%hardware can be found \href{Purchasing}{here}.
%
%\section{Overview}\label{overview}

Following the ARTIQ model, an experiment consists of a core device
(master) -- typically either a \url{Metlino} or \url{Kasli} --
controlling multiple slave devices in real time using ARTIQ's
\href{https://github.com/m-labs/artiq/wiki/DRTIO}{distributed real-time
IO} (DRTIO) protocol. DRTIO provides both gigabit communication links
and time distribution over copper cable or optical fibres. It
synchronises all device clocks, ensuring they have deterministic phase
relationships, and enables nanosecond timing resolution for input and
output events across all devices in the experiment. More detailed
information about communication between devices and time distribution
inside Sinara can be found \href{SinaraClocking}{here}.\\

Sinara uses two main form factors for hardware requiring real-time
control: microTCA (uTCA) and Eurocard Extension Modules (EEM). Non
real-time hardware is typically connected to the host PC using ethernet.\\

MicroTCA (uTCA) is Sinara's preferred form factor for high performance
hardware with high-speed data converters requiring deterministic phase
control, such as the \href{Sayma}{\emph{Sayma}} Smart Arbitrary Waveform
Generator (SAWG). Information about uTCA hardware, including a list of
parts needed to build a Sinara uTCA crate can be found
\href{uTCA}{here}.\\

EEMs provide a lower cost, simpler platform than uTCA for hardware that
requires real-time control, but not bandwidth or complexity of uTCA
hardware.\\

Extension modules connect to a carrier, such as \url{Kasli} or the
\href{VHDCICarrier}{VHDCI carrier}, which provides power and DRTIO. They
are designed to be mounted either in stand-alone enclosures, or in a
rack with a carrier, and connect to the carrier via ribbon cable. More
details about the extension module standard can be found
\href{EEM}{here}.\\

uTCA hardware interfaces with the extension modules either directly,
using a \href{VHDCICarrier}{VHDCI carrier}, or indirectly, using a
\url{Kasli} DRTIO slave.
350 changes: 197 additions & 153 deletions ARTIQ_EE/PCB_Sayma_AMC/Manual/tex/wiki_sayma.tex
Original file line number Diff line number Diff line change
@@ -1,153 +1,197 @@
\section{Sayma Smart Arbitrary Waveform
Generator}\label{sayma-smart-arbitrary-waveform-generator}

Sayma is a smart arbitrary waveform generator, providing 8 channels of
1.2 GSPS 16-bit DACs (2.4 GHz DAC clock) and 125 MSPS 16-bit ADCs. It
consists of an AMC, providing the high-speed digital logic, and a RTM,
holding the data converters and analog components.

The design files are located in
\href{https://github.com/m-labs/sinara/tree/master/ARTIQ_EE/PCB_Sayma_AMC}{ARTIQ\_EE/PCB\_Sayma\_AMC}
and
\href{https://github.com/m-labs/sinara/tree/master/ARTIQ_EE/PCB_Sayma_RTM}{ARTIQ\_EE/PCB\_Sayma\_RTM}
and, the AMC schematic is
\href{https://github.com/m-labs/sinara/blob/master/ARTIQ_EE/Sayma_AMC.pdf}{here}
and the RTM schematic is
\href{https://github.com/m-labs/sinara/blob/master/ARTIQ_EE/Sayma_RTM.pdf}{here}.
The PCBs are double width, mid height AMC module. Sayma AMC

\subsection{Features}\label{features}

\begin{itemize}

\item
May be used in a uTCA rack or stand-alone operation with fibre-based
DRTIO link
\item
Analog input and output front-ends provided by plug-in
\href{SaymaAFE}{analog front-end modules} (eg BaseMod) for maximum
flexibility.
\item
Extremely flexible \href{SinaraClocking}{clocking options}
\item
Flexible feedback to SAWG parameters planned. Specification
\href{Servo}{here}.
\end{itemize}

\subsection{Key AMC Components}\label{key-amc-components}

\begin{itemize}

\item
\textbf{FPGA}: XCKU040-1FFVA1156C Kintex Ultrascale, 520 I/O, 530K
Logic Cells, Speed Grade 1, 20 GTH transceivers (up to 16.3 Gb/s) --
motivation for this FPGA choice is
\href{https://github.com/m-labs/sinara/wiki/artiq_hardware\#recommendation}{here}
\item
\textbf{DRAM}: MT41K256M16TW-107:P, DDR3, 32 MB x 16 x 8 banks = 4 GB
\item
\textbf{clock recovery}: Si5324 is a precision clock multiplier and
jitter attenuator
\end{itemize}

\subsection{Key RTM Components}\label{key-rtm-components}

\begin{itemize}

\item
\textbf{DAC}: AD9154 4-channel high-speed data converter

\begin{itemize}

\item
data rate is 1.2 GS/s at 16-bit
\item
clock is up to 2.4 GHz (1x, 2x, 4x and 8x interpolating modes)
\item
supports mix-mode to emphasize power in 3rd Nyquist Zone
\item
interface is 8-lane JESD204B (subclass 1)
\item
power consumption is 2.11 W
\item
each Sayma has 2 AD9154
\end{itemize}
\item
\textbf{ADC}: AD9656 is a 4-channel high-speed digitizer

\begin{itemize}

\item
data rate is 125 MS/s at 16-bit
\item
clock is up to 125 MHz
\item
650 MHz analog bandwidth
\item
interface is 8-lane, 8 Gb/s per lane, JESD204B (subclass 1)
\item
each Sayma has 2 AD9656
\end{itemize}
\item
\textbf{clock generation}: (summarized \href{SinaraClocking}{here})

\begin{itemize}

\item
Sayma has several distinct clock domains

\begin{itemize}

\item
DAC, JESB204B output clock
\item
ADC, JESD204B input clock
\item
LO for analog mezzanines
\end{itemize}
\item
These clocks may be generated using a low phase noise
\href{ClockMezzanines}{Clock Mezzanine} PCB. A single Clock
Mezzanine can be shared by several Sayma in a uTCA crate using
{[}Baikal{]} PCB and an RTM RF backplane. Alternately, each Sayma
can have its own distinct Clock Mezzanine (local generation).
\end{itemize}
\item
\textbf{clock distribution}

\begin{itemize}

\item
HMC7043 SPI 14-Output Fanout Buffer for JESD204B
\item
HMC830 SPI fractional-N PLL
\end{itemize}
\item
\textbf{calibration ADC}: AD7194BCPZ is a 20-bit ADC for
monitoring/calibration
\end{itemize}

\subsection{Transceiver/connector
usage}\label{transceiverconnector-usage}

\begin{itemize}

\item
SFP1: DRTIO downstream
\item
SFP2: DRTIO downstream
\item
SATA1: DRTIO upstream (different bitstream probably)
\item
SATA2 (swapped): DRTIO downstream
\item
FAT\_PIPE1 (FABRICD): DRTIO upstream
\item
FAT\_PIPE2 (FABRICE): not used
\item
FMC:
\item
LA: FMC DIO32: TTL IO
\end{itemize}


\section{Sayma}

Sayma is a hardware that supports M-Lab's Smart Arbitrary Waveform Generator(\href{http://m-labs.hk/artiq/manual-master/core_drivers_reference.html?highlight=sawg#module-artiq.coredevice.sawg}{SAWG}) gateware.
Provide 8 channels of
1.2 GSPS 16-bit DACs (2.4 GHz DAC clock) and 125 MSPS 16-bit ADCs. It
consists of an AMC, providing the high-speed digital logic, and a RTM,
holding the data converters and analog components.

The design files are located in
\href{https://github.com/m-labs/sinara/tree/master/ARTIQ_EE/PCB_Sayma_AMC}{ARTIQ\_EE/PCB\_Sayma\_AMC}
and
\href{https://github.com/m-labs/sinara/tree/master/ARTIQ_EE/PCB_Sayma_RTM}{ARTIQ\_EE/PCB\_Sayma\_RTM}
and, the AMC schematic is
\href{https://github.com/m-labs/sinara/blob/master/ARTIQ_EE/Sayma_AMC.pdf}{here}
and the RTM schematic is
\href{https://github.com/m-labs/sinara/blob/master/ARTIQ_EE/Sayma_RTM.pdf}{here}.
The PCBs are double width, mid height AMC module. Sayma AMC

\subsection{Features}\label{features}

\begin{itemize}

\item
May be used in a uTCA rack or stand-alone operation with fibre-based
DRTIO link
\item
Analog input and output front-ends provided by plug-in
\href{https://github.com/m-labs/sinara/wiki/SaymaAFE}{AFE} modules (eg BaseMod) for maximum
flexibility.
\item
Extremely flexible \href{https://github.com/m-labs/sinara/wiki/SinaraClocking}{clocking options}
\item
Flexible feedback to SAWG parameters planned. Specification
\href{https://github.com/m-labs/sinara/wiki/Servo}{here}.
\end{itemize}

\subsection{Key AMC Components}\label{key-amc-components}


\noindent

\textbf{Programmable resources:}

\begin{itemize}
\item Xilinx Kintex UltraScale – XCKU040-1FFVA-1156C FPGA 20 I/O, 530K
Logic Cells
\begin{itemize}
\item speed grade: -1
\item 20 GTH transceivers (Max Preformance 16.3 Gb/s)
\end{itemize}
\item MMC: LPC17762984
\end{itemize}

\textbf{Memory:}

\begin{itemize}
\item 512Mb DDR3 SDRAM (32-bit interface), 800MHz (clock)
\item 1Gb DDR3 SDRAM (64-bit interface), 800MHz (clock)
\item SPI Flash for FPGA configuration. Accessible by MMC
\item SPI Flash for user data storage
\item EEPROM with MAC and unique ID

\end{itemize}

\textbf{Connectivity:}

\begin{itemize}
\item 1 high pin count (HPC) FMC slot for single width mezzanine card
\item Micro-USB UART connected to FPGA or MMC
\item Stand-alone 12V power connector
\item MGT (Multi-Gigabit Transceiver) connected to:
\begin{itemize}
% \item FMC x1
\item RTM x16
\item Fat\_Pipe1 x2
% \item AMC P2P x4
% \item Port 0 – possibility connected to SATA
\item SFP x2
\end{itemize}
% \item RTM connector with 8 GTP routed to it. Compatible with Sayma RTM module.
\item Port 0 – possibility connected to SATA
\item RTM connector compatible with Sayma RTM module

\end{itemize}

\textbf{Supply:}

\begin{itemize}
\item Monitoring of voltage and Power supply for RTM 12V and FMC 12V
\item FMC VADJ fixed to 1V8
\item Monitoring current of all FMC buses
\item Stand-alone power connectore
% \item Czy Exar monitoruje powera?

\end{itemize}


\textbf{Clocking:}

\begin{itemize}
\item Clock recovery Si5324 is a precision clock multiplier andjitter attenuator
\item UFL CLK input
\item SMA CLK output


\end{itemize}


\textbf{Other:}

\begin{itemize}
\item Temperature, voltage and current monitoring for critical power buses
\item Temperature monitoring: FMC1, supply, FPGA core, DDR memory
\item JTAG multiplexer (SCANSTA) for FMC access, local JTAG port and remote debug/Chipscope via Ethernet

\end{itemize}

\subsection{Key RTM Components}\label{key-rtm-components}
\todo[inline]{not sure if it should be here? only in RTM doc?}
\begin{itemize}

\item
\textbf{DAC}: AD9154 4-channel high-speed data converter

\begin{itemize}

\item
data rate is 1.2 GS/s at 16-bit
\item
clock is up to 2.4 GHz (1x, 2x, 4x and 8x interpolating modes)
\item
supports mix-mode to emphasize power in 3rd Nyquist Zone
\item
interface is 8-lane JESD204B (subclass 1)
\item
power consumption is 2.11 W
\item
each Sayma has 2 AD9154
\end{itemize}
\item
\textbf{ADC}: AD9656 is a 4-channel high-speed digitizer

\begin{itemize}

\item
data rate is 125 MS/s at 16-bit
\item
clock is up to 125 MHz
\item
650 MHz analog bandwidth
\item
interface is 8-lane, 8 Gb/s per lane, JESD204B (subclass 1)
\item
each Sayma has 2 AD9656
\end{itemize}
\item
\textbf{clock generation}: (summarized \href{SinaraClocking}{here})

\begin{itemize}

\item
Sayma has several distinct clock domains

\begin{itemize}

\item
DAC, JESB204B output clock
\item
ADC, JESD204B input clock
\item
LO for analog mezzanines
\end{itemize}
\item
These clocks may be generated using a low phase noise
\href{ClockMezzanines}{Clock Mezzanine} PCB. A single Clock
Mezzanine can be shared by several Sayma in a uTCA crate using
{[}Baikal{]} PCB and an RTM RF backplane. Alternately, each Sayma
can have its own distinct Clock Mezzanine (local generation).
\end{itemize}
\item
\textbf{clock distribution}

\begin{itemize}

\item
HMC7043 SPI 14-Output Fanout Buffer for JESD204B
\item
HMC830 SPI fractional-N PLL
\end{itemize}
\item
\textbf{calibration ADC}: AD7194BCPZ is a 20-bit ADC for
monitoring/calibration
\end{itemize}




147 changes: 74 additions & 73 deletions ARTIQ_EE/PCB_Sayma_AMC/Manual/tex/wiki_utca.tex
Original file line number Diff line number Diff line change
@@ -1,73 +1,74 @@
\section{Overview}\label{overview}

MicroTCA (uTCA) is Sinara's preferred form-factor for hardware with
high-speed data converters requiring deterministic phase control, such
as the \href{Sayma}{\emph{Sayma}} 2.4 GSPS smart arbitrary waveform
generator (SAWG).

uTCA is a modular, open standard originally developed by the
telecommunications industry. It allows a single rack master -- the Micro
TCA Carrier Hub (MCH) -- to control multiple slave boards, known as
Advanced Mezzanine Cards (AMCs) via a high-speed digital backplane. uTCA
chassis and backplanes are available commercially of the shelf (COTS).

We make use of the most recent extension to the uTCA standard, uTCA.4.
Originating in the high-energy and particle physics (HEPP) community,
uTCA.4 introduces rear-transition modules (RTMs) along with a second
backplane for low-noise RF signals (RFBP). Each RTM connects to an AMC
(one RTM per AMC). Typically, the AMCs hold FPGAs and other high-speed
digital hardware, communicating with the MCH via gigabit serial links
over the AMC backplane. The RTMs hold data converters and other
low-noise analog components, controlled by the corresponding AMC. The
RFBP provides low-noise clocks and local oscillators (LOs). The RTMs and
RFBP are screened from the AMCs to minimise interference from the
high-speed digital logic.

\begin{figure}[htbp!]
\centering
\includegraphics[width=15cm]{img/MTCA_Front.jpg}
\caption{Micro TCA chassis with 3 Sayma AMC modules inserted}
\end{figure}

(above) Micro TCA chassis with 3 Sayma AMC modules inserted.

Micro TCA chassis with 4 RTM modules inserted. One of them with 4
BaseMod AFE mezzanines installed.

\begin{figure}[htbp!]
\centering
\includegraphics[width=15cm]{img/MTCA_Back.jpg}
\caption{Micro TCA chassis with 4 RTM modules inserted. One of them has
4 BaseMod AFE mezzanines installed.}
\end{figure}

\section{uTCA.4 RF Backplane}\label{utca.4-rf-backplane}

\href{http://mtca.desy.de/sites/site_mtca/content/e172206/e205636/e212584/e248086/uRFB_concept_Datasheet_19.12.2014_eng.pdf}{RF
BP datasheet}
\href{http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=7097413\&tag=1}{RF
BP measurements}

\section{uTCA in Sinara}\label{utca-in-sinara}

\href{Metlino}{\emph{Metlino}} has been developed as an MCH optimised
for use in Sinara. It can either be the ARTIQ master or a slave,
connected to the master via DRTIO.

uTCA hardware interfaces with the extension modules either directly,
using a \href{VHDCICarrier}{VHDCI carrier}, or indirectly, using a Kasli
DRTIO slave.

To do: * Some images to illustrate what uTCA systems look like * Explain
how Baikal etc fit in * Add BP schematics that show what the
connectivity is * Any more useful information?

\section{uTCA parts and suppliers}\label{utca-parts-and-suppliers}

Add parts and suppliers from the issues list\ldots{}

\section{Schematic / Layout Viewer}\label{schematic-layout-viewer}

Mentor has a free tool called
\href{https://www.mentor.com/pcb/downloads/visecad-viewer/}{visECAD
Viewer}.
\section{uTCA.4 Overview}

MicroTCA (uTCA) is Sinara's preferred form-factor for hardware with
high-speed data converters requiring deterministic phase control, such
as the \href{Sayma}{\emph{Sayma}} 2.4 GSPS smart arbitrary waveform
generator (SAWG).

uTCA is a modular, open standard originally developed by the
telecommunications industry. It allows a single rack master -- the Micro
TCA Carrier Hub (MCH) -- to control multiple slave boards, known as
Advanced Mezzanine Cards (AMCs) via a high-speed digital backplane. uTCA
chassis and backplanes are available commercially of the shelf (COTS).

We make use one of the most recent extension to the uTCA standard, uTCA.4.
Originating in the high-energy and particle physics (HEPP) community,
uTCA.4 introduces rear-transition modules (RTMs) along with a second
backplane for low-noise RF signals (RFBP). Each RTM connects to an AMC
(one RTM per AMC). Typically, the AMCs hold FPGAs and other high-speed
digital hardware, communicating with the MCH via gigabit serial links
over the AMC backplane. The RTMs hold data converters and other
low-noise analog components, controlled by the corresponding AMC. The
RFBP provides low-noise clocks and local oscillators (LOs). The RTMs and
RFBP are screened from the AMCs to minimise interference from the
high-speed digital logic.

\begin{figure}[htbp!]
\centering
\includegraphics[width=15cm]{img/MTCA_Front1.jpg}
\caption{Micro TCA chassis with 3 Sayma AMC modules inserted}
\end{figure}

\todo[inline]{New Figure: add photo of Sayma\_AMC attached to Sayma\_RTM sitting on bench so how they're connected is clear.}

(above) Micro TCA chassis with 3 Sayma AMC modules inserted.

Micro TCA chassis with 4 RTM modules inserted. One of them with 4
BaseMod AFE mezzanines installed.

\begin{figure}[htbp!]
\centering
\includegraphics[width=15cm]{img/MTCA_Back.jpg}
\caption{Micro TCA chassis with 4 RTM modules inserted. One of them has
4 BaseMod AFE mezzanines installed.}
\end{figure}


\href{http://www.nateurope.com/products/NAT-LLRF-Backplane.html}{RF
BP datasheet}



\section{uTCA parts and suppliers}\label{utca-parts-and-suppliers}

\begin{itemize}
\item NAT AC 600D, qty 1
\item NAT MCH-Basic v3.5, mid-size front panel, qty 1
\item NAT Native-R5, qty 1
\end{itemize}

\section{Schematic / Layout Viewer}\label{schematic-layout-viewer}


Hardware was designed under Mentor Graphics Xpedition Enterprise and Altium Designer CAD tools.
Project resources are in two separate folders:
\begin{itemize}
\item ARTIQ\_EE folder is for designs made with the Mentor Graphics Xpedition Enterprise CAD tool.
\item ARTIQ\_ALTIUM folder is for designs made with Altium Designer CAD tool.
\end{itemize}
Read-only access to PCB schematics and layout designs is possible using free tools.\\
Mentor has a free tool called
\href{https://www.mentor.com/pcb/downloads/visecad-viewer/}{visECAD
Viewer}.\\
Altium has a free tool called
\href{http://www.altium.com/altium-designer-viewer}{Altium Designer viewer}

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