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base repository: azonenberg/yosys
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head repository: azonenberg/yosys
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compare: b72a7e110455
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  • 2 commits
  • 20 files changed
  • 2 contributors

Commits on Apr 12, 2017

  1. Squelch trailing whitespace

    ldoolitt authored and cliffordwolf committed Apr 12, 2017
    Copy the full SHA
    2021dde View commit details
  2. Copy the full SHA
    b72a7e1 View commit details
4 changes: 2 additions & 2 deletions examples/cmos/counter_tb.v
Original file line number Diff line number Diff line change
@@ -12,7 +12,7 @@ module counter_tb;
# 4 reset = 0;
# 6 $finish;
end

/* Make enable with period of 8 and 6,7 low */
reg en = 1;
always begin
@@ -25,7 +25,7 @@ module counter_tb;
/* Make a regular pulsing clock. */
reg clk = 0;
always #1 clk = !clk;

/* UUT */
wire [2:0] count;
counter c1 (clk, reset, en, count);
2 changes: 1 addition & 1 deletion examples/cmos/testbench_digital.sh
Original file line number Diff line number Diff line change
@@ -4,7 +4,7 @@ set -ex

# iverlog simulation
echo "Doing Verilog simulation with iverilog"
iverilog -o counter_tb counter.v counter_tb.v
iverilog -o counter_tb counter.v counter_tb.v
./counter_tb; gtkwave counter_tb.gtkw &

# yosys synthesis
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