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Refactored GreenPAK4 cells_sim into cells_sim_ams and cells_sim_digital
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azonenberg committed Aug 5, 2017
1 parent d527ed9 commit b735a0f
Showing 4 changed files with 451 additions and 428 deletions.
2 changes: 2 additions & 0 deletions techlibs/greenpak4/Makefile.inc
Original file line number Diff line number Diff line change
@@ -6,4 +6,6 @@ OBJS += techlibs/greenpak4/greenpak4_dffinv.o
$(eval $(call add_share_file,share/greenpak4,techlibs/greenpak4/cells_latch.v))
$(eval $(call add_share_file,share/greenpak4,techlibs/greenpak4/cells_map.v))
$(eval $(call add_share_file,share/greenpak4,techlibs/greenpak4/cells_sim.v))
$(eval $(call add_share_file,share/greenpak4,techlibs/greenpak4/cells_sim_ams.v))
$(eval $(call add_share_file,share/greenpak4,techlibs/greenpak4/cells_sim_digital.v))
$(eval $(call add_share_file,share/greenpak4,techlibs/greenpak4/gp_dff.lib))
431 changes: 3 additions & 428 deletions techlibs/greenpak4/cells_sim.v
Original file line number Diff line number Diff line change
@@ -1,57 +1,9 @@
`timescale 1ns/1ps

module GP_2LUT(input IN0, IN1, output OUT);
parameter [3:0] INIT = 0;
assign OUT = INIT[{IN1, IN0}];
endmodule

module GP_3LUT(input IN0, IN1, IN2, output OUT);
parameter [7:0] INIT = 0;
assign OUT = INIT[{IN2, IN1, IN0}];
endmodule

module GP_4LUT(input IN0, IN1, IN2, IN3, output OUT);
parameter [15:0] INIT = 0;
assign OUT = INIT[{IN3, IN2, IN1, IN0}];
endmodule

module GP_ABUF(input wire IN, output wire OUT);

assign OUT = IN;

//must be 1, 5, 20, 50
//values >1 only available with Vdd > 2.7V
parameter BANDWIDTH_KHZ = 1;

//cannot simulate mixed signal IP

endmodule

module GP_ACMP(input wire PWREN, input wire VIN, input wire VREF, output reg OUT);
`include "cells_sim_ams.v"
`include "cells_sim_digital.v"

parameter BANDWIDTH = "HIGH";
parameter VIN_ATTEN = 1;
parameter VIN_ISRC_EN = 0;
parameter HYSTERESIS = 0;

initial OUT = 0;

//cannot simulate mixed signal IP

endmodule

module GP_BANDGAP(output reg OK);
parameter AUTO_PWRDN = 1;
parameter CHOPPER_EN = 1;
parameter OUT_DELAY = 100;

//cannot simulate mixed signal IP

endmodule

module GP_CLKBUF(input wire IN, output wire OUT);
assign OUT = IN;
endmodule
//Cells still in this file have INCOMPLETE simulation models, need to finish them

module GP_COUNT8(input CLK, input wire RST, output reg OUT, output reg[7:0] POUT);

@@ -129,14 +81,6 @@ module GP_COUNT14_ADV(input CLK, input RST, output reg OUT,

endmodule

module GP_DAC(input[7:0] DIN, input wire VREF, output reg VOUT);

initial VOUT = 0;

//analog hard IP is not supported for simulation

endmodule

module GP_DCMP(input[7:0] INP, input[7:0] INN, input CLK, input PWRDN, output reg GREATER, output reg EQUAL);
parameter PWRDN_SYNC = 1'b0;
parameter CLK_EDGE = "RISING";
@@ -159,237 +103,6 @@ module GP_DCMP(input[7:0] INP, input[7:0] INN, input CLK, input PWRDN, output re

endmodule

module GP_DCMPREF(output reg[7:0]OUT);
parameter[7:0] REF_VAL = 8'h00;
initial OUT = REF_VAL;
endmodule

module GP_DCMPMUX(input[1:0] SEL, input[7:0] IN0, input[7:0] IN1, input[7:0] IN2, input[7:0] IN3, output reg[7:0] OUTA, output reg[7:0] OUTB);

always @(*) begin
case(SEL)
2'd00: begin
OUTA <= IN0;
OUTB <= IN3;
end

2'd01: begin
OUTA <= IN1;
OUTB <= IN2;
end

2'd02: begin
OUTA <= IN2;
OUTB <= IN1;
end

2'd03: begin
OUTA <= IN3;
OUTB <= IN0;
end

endcase
end
endmodule

module GP_DELAY(input IN, output reg OUT);

parameter DELAY_STEPS = 1;
parameter GLITCH_FILTER = 0;

initial OUT = 0;

generate

//TODO: These delays are PTV dependent! For now, hard code 3v3 timing
//Change simulation-mode delay depending on global Vdd range (how to specify this?)
always @(*) begin
case(DELAY_STEPS)
1: #166 OUT = IN;
2: #318 OUT = IN;
2: #471 OUT = IN;
3: #622 OUT = IN;
default: begin
$display("ERROR: GP_DELAY must have DELAY_STEPS in range [1,4]");
$finish;
end
endcase
end

endgenerate

endmodule

module GP_DFF(input D, CLK, output reg Q);
parameter [0:0] INIT = 1'bx;
initial Q = INIT;
always @(posedge CLK) begin
Q <= D;
end
endmodule

module GP_DFFI(input D, CLK, output reg nQ);
parameter [0:0] INIT = 1'bx;
initial nQ = INIT;
always @(posedge CLK) begin
nQ <= ~D;
end
endmodule

module GP_DFFR(input D, CLK, nRST, output reg Q);
parameter [0:0] INIT = 1'bx;
initial Q = INIT;
always @(posedge CLK, negedge nRST) begin
if (!nRST)
Q <= 1'b0;
else
Q <= D;
end
endmodule

module GP_DFFRI(input D, CLK, nRST, output reg nQ);
parameter [0:0] INIT = 1'bx;
initial nQ = INIT;
always @(posedge CLK, negedge nRST) begin
if (!nRST)
nQ <= 1'b1;
else
nQ <= ~D;
end
endmodule

module GP_DFFS(input D, CLK, nSET, output reg Q);
parameter [0:0] INIT = 1'bx;
initial Q = INIT;
always @(posedge CLK, negedge nSET) begin
if (!nSET)
Q <= 1'b1;
else
Q <= D;
end
endmodule

module GP_DFFSI(input D, CLK, nSET, output reg nQ);
parameter [0:0] INIT = 1'bx;
initial nQ = INIT;
always @(posedge CLK, negedge nSET) begin
if (!nSET)
nQ <= 1'b0;
else
nQ <= ~D;
end
endmodule

module GP_DFFSR(input D, CLK, nSR, output reg Q);
parameter [0:0] INIT = 1'bx;
parameter [0:0] SRMODE = 1'bx;
initial Q = INIT;
always @(posedge CLK, negedge nSR) begin
if (!nSR)
Q <= SRMODE;
else
Q <= D;
end
endmodule

module GP_DFFSRI(input D, CLK, nSR, output reg nQ);
parameter [0:0] INIT = 1'bx;
parameter [0:0] SRMODE = 1'bx;
initial nQ = INIT;
always @(posedge CLK, negedge nSR) begin
if (!nSR)
nQ <= ~SRMODE;
else
nQ <= ~D;
end
endmodule

module GP_DLATCH(input D, input nCLK, output reg Q);
parameter [0:0] INIT = 1'bx;
initial Q = INIT;
always @(*) begin
if(!nCLK)
Q <= D;
end
endmodule

module GP_DLATCHI(input D, input nCLK, output reg nQ);
parameter [0:0] INIT = 1'bx;
initial nQ = INIT;
always @(*) begin
if(!nCLK)
nQ <= ~D;
end
endmodule

module GP_DLATCHR(input D, input nCLK, input nRST, output reg Q);
parameter [0:0] INIT = 1'bx;
initial Q = INIT;
always @(*) begin
if(!nRST)
Q <= 1'b0;
else if(!nCLK)
Q <= D;
end
endmodule

module GP_DLATCHRI(input D, input nCLK, input nRST, output reg nQ);
parameter [0:0] INIT = 1'bx;
initial nQ = INIT;
always @(*) begin
if(!nRST)
nQ <= 1'b1;
else if(!nCLK)
nQ <= ~D;
end
endmodule

module GP_DLATCHS(input D, input nCLK, input nSET, output reg Q);
parameter [0:0] INIT = 1'bx;
initial Q = INIT;
always @(*) begin
if(!nSET)
Q <= 1'b1;
else if(!nCLK)
Q <= D;
end
endmodule

module GP_DLATCHSI(input D, input nCLK, input nSET, output reg nQ);
parameter [0:0] INIT = 1'bx;
initial nQ = INIT;
always @(*) begin
if(!nSET)
nQ <= 1'b0;
else if(!nCLK)
nQ <= ~D;
end
endmodule

module GP_DLATCHSR(input D, input nCLK, input nSR, output reg Q);
parameter [0:0] INIT = 1'bx;
parameter[0:0] SRMODE = 1'bx;
initial Q = INIT;
always @(*) begin
if(!nSR)
Q <= SRMODE;
else if(!nCLK)
Q <= D;
end
endmodule

module GP_DLATCHSRI(input D, input nCLK, input nSR, output reg nQ);
parameter [0:0] INIT = 1'bx;
parameter[0:0] SRMODE = 1'bx;
initial nQ = INIT;
always @(*) begin
if(!nSR)
nQ <= ~SRMODE;
else if(!nCLK)
nQ <= ~D;
end
endmodule

module GP_EDGEDET(input IN, output reg OUT);

parameter EDGE_DIRECTION = "RISING";
@@ -400,107 +113,6 @@ module GP_EDGEDET(input IN, output reg OUT);

endmodule

module GP_IBUF(input IN, output OUT);
assign OUT = IN;
endmodule

module GP_IOBUF(input IN, input OE, output OUT, inout IO);
assign OUT = IO;
assign IO = OE ? IN : 1'bz;
endmodule

module GP_INV(input IN, output OUT);
assign OUT = ~IN;
endmodule

module GP_LFOSC(input PWRDN, output reg CLKOUT);

parameter PWRDN_EN = 0;
parameter AUTO_PWRDN = 0;
parameter OUT_DIV = 1;

initial CLKOUT = 0;

//auto powerdown not implemented for simulation
//output dividers not implemented for simulation

always begin
if(PWRDN)
CLKOUT = 0;
else begin
//half period of 1730 Hz
#289017;
CLKOUT = ~CLKOUT;
end
end

endmodule

module GP_OBUF(input IN, output OUT);
assign OUT = IN;
endmodule

module GP_OBUFT(input IN, input OE, output OUT);
assign OUT = OE ? IN : 1'bz;
endmodule

module GP_PGA(input wire VIN_P, input wire VIN_N, input wire VIN_SEL, output reg VOUT);

parameter GAIN = 1;
parameter INPUT_MODE = "SINGLE";

initial VOUT = 0;

//cannot simulate mixed signal IP

endmodule

module GP_PGEN(input wire nRST, input wire CLK, output reg OUT);
initial OUT = 0;
parameter PATTERN_DATA = 16'h0;
parameter PATTERN_LEN = 5'd16;

reg[3:0] count = 0;
always @(posedge CLK) begin
if(!nRST)
OUT <= PATTERN_DATA[0];

else begin
count <= count + 1;
OUT <= PATTERN_DATA[count];

if( (count + 1) == PATTERN_LEN)
count <= 0;
end
end

endmodule

module GP_PWRDET(output reg VDD_LOW);
initial VDD_LOW = 0;
endmodule

module GP_POR(output reg RST_DONE);
parameter POR_TIME = 500;

initial begin
RST_DONE = 0;

if(POR_TIME == 4)
#4000;
else if(POR_TIME == 500)
#500000;
else begin
$display("ERROR: bad POR_TIME for GP_POR cell");
$finish;
end

RST_DONE = 1;

end

endmodule

module GP_RCOSC(input PWRDN, output reg CLKOUT_HARDIP, output reg CLKOUT_FABRIC);

parameter PWRDN_EN = 0;
@@ -567,29 +179,6 @@ module GP_RINGOSC(input PWRDN, output reg CLKOUT_HARDIP, output reg CLKOUT_FABRI

endmodule

module GP_SHREG(input nRST, input CLK, input IN, output OUTA, output OUTB);

parameter OUTA_TAP = 1;
parameter OUTA_INVERT = 0;
parameter OUTB_TAP = 1;

reg[15:0] shreg = 0;

always @(posedge CLK, negedge nRST) begin

if(!nRST)
shreg = 0;

else
shreg <= {shreg[14:0], IN};

end

assign OUTA = (OUTA_INVERT) ? ~shreg[OUTA_TAP - 1] : shreg[OUTA_TAP - 1];
assign OUTB = shreg[OUTB_TAP - 1];

endmodule

module GP_SPI(
input SCK,
inout SDAT,
@@ -625,17 +214,3 @@ module GP_SYSRESET(input RST);
//cannot simulate whole system reset

endmodule

module GP_VDD(output OUT);
assign OUT = 1;
endmodule

module GP_VREF(input VIN, output reg VOUT);
parameter VIN_DIV = 1;
parameter VREF = 0;
//cannot simulate mixed signal IP
endmodule

module GP_VSS(output OUT);
assign OUT = 0;
endmodule
89 changes: 89 additions & 0 deletions techlibs/greenpak4/cells_sim_ams.v
Original file line number Diff line number Diff line change
@@ -0,0 +1,89 @@
`timescale 1ns/1ps

/*
This file contains analog / mixed signal cells, or other things that are not possible to fully model
in behavioral Verilog.
It also contains some stuff like oscillators that use non-synthesizeable constructs such as delays.
TODO: do we want a third file for those cells?
*/

module GP_ABUF(input wire IN, output wire OUT);

assign OUT = IN;

//must be 1, 5, 20, 50
//values >1 only available with Vdd > 2.7V
parameter BANDWIDTH_KHZ = 1;

endmodule

module GP_ACMP(input wire PWREN, input wire VIN, input wire VREF, output reg OUT);

parameter BANDWIDTH = "HIGH";
parameter VIN_ATTEN = 1;
parameter VIN_ISRC_EN = 0;
parameter HYSTERESIS = 0;

initial OUT = 0;

endmodule

module GP_BANDGAP(output reg OK);
parameter AUTO_PWRDN = 1;
parameter CHOPPER_EN = 1;
parameter OUT_DELAY = 100;

endmodule

module GP_DAC(input[7:0] DIN, input wire VREF, output reg VOUT);

initial VOUT = 0;

//analog hard IP is not supported for simulation

endmodule

module GP_LFOSC(input PWRDN, output reg CLKOUT);

parameter PWRDN_EN = 0;
parameter AUTO_PWRDN = 0;
parameter OUT_DIV = 1;

initial CLKOUT = 0;

//auto powerdown not implemented for simulation
//output dividers not implemented for simulation

always begin
if(PWRDN)
CLKOUT = 0;
else begin
//half period of 1730 Hz
#289017;
CLKOUT = ~CLKOUT;
end
end

endmodule

module GP_PGA(input wire VIN_P, input wire VIN_N, input wire VIN_SEL, output reg VOUT);

parameter GAIN = 1;
parameter INPUT_MODE = "SINGLE";

initial VOUT = 0;

//cannot simulate mixed signal IP

endmodule

module GP_PWRDET(output reg VDD_LOW);
initial VDD_LOW = 0;
endmodule

module GP_VREF(input VIN, output reg VOUT);
parameter VIN_DIV = 1;
parameter VREF = 0;
//cannot simulate mixed signal IP
endmodule
357 changes: 357 additions & 0 deletions techlibs/greenpak4/cells_sim_digital.v
Original file line number Diff line number Diff line change
@@ -0,0 +1,357 @@
`timescale 1ns/1ps

/*
This file contains simulation models for GreenPAK cells which are possible to fully model using synthesizeable
behavioral Verilog constructs only.
*/

module GP_2LUT(input IN0, IN1, output OUT);
parameter [3:0] INIT = 0;
assign OUT = INIT[{IN1, IN0}];
endmodule

module GP_3LUT(input IN0, IN1, IN2, output OUT);
parameter [7:0] INIT = 0;
assign OUT = INIT[{IN2, IN1, IN0}];
endmodule

module GP_4LUT(input IN0, IN1, IN2, IN3, output OUT);
parameter [15:0] INIT = 0;
assign OUT = INIT[{IN3, IN2, IN1, IN0}];
endmodule

module GP_CLKBUF(input wire IN, output wire OUT);
assign OUT = IN;
endmodule

module GP_DCMPREF(output reg[7:0]OUT);
parameter[7:0] REF_VAL = 8'h00;
initial OUT = REF_VAL;
endmodule

module GP_DCMPMUX(input[1:0] SEL, input[7:0] IN0, input[7:0] IN1, input[7:0] IN2, input[7:0] IN3, output reg[7:0] OUTA, output reg[7:0] OUTB);

always @(*) begin
case(SEL)
2'd00: begin
OUTA <= IN0;
OUTB <= IN3;
end

2'd01: begin
OUTA <= IN1;
OUTB <= IN2;
end

2'd02: begin
OUTA <= IN2;
OUTB <= IN1;
end

2'd03: begin
OUTA <= IN3;
OUTB <= IN0;
end

endcase
end
endmodule

module GP_DELAY(input IN, output reg OUT);

parameter DELAY_STEPS = 1;
parameter GLITCH_FILTER = 0;

initial OUT = 0;

generate

if(GLITCH_FILTER) begin
initial begin
$display("ERROR: GP_DELAY glitch filter mode not implemented");
$finish;
end
end

//TODO: These delays are PTV dependent! For now, hard code 3v3 timing
//Change simulation-mode delay depending on global Vdd range (how to specify this?)
always @(*) begin
case(DELAY_STEPS)
1: #166 OUT = IN;
2: #318 OUT = IN;
2: #471 OUT = IN;
3: #622 OUT = IN;
default: begin
$display("ERROR: GP_DELAY must have DELAY_STEPS in range [1,4]");
$finish;
end
endcase
end

endgenerate

endmodule

module GP_DFF(input D, CLK, output reg Q);
parameter [0:0] INIT = 1'bx;
initial Q = INIT;
always @(posedge CLK) begin
Q <= D;
end
endmodule

module GP_DFFI(input D, CLK, output reg nQ);
parameter [0:0] INIT = 1'bx;
initial nQ = INIT;
always @(posedge CLK) begin
nQ <= ~D;
end
endmodule

module GP_DFFR(input D, CLK, nRST, output reg Q);
parameter [0:0] INIT = 1'bx;
initial Q = INIT;
always @(posedge CLK, negedge nRST) begin
if (!nRST)
Q <= 1'b0;
else
Q <= D;
end
endmodule

module GP_DFFRI(input D, CLK, nRST, output reg nQ);
parameter [0:0] INIT = 1'bx;
initial nQ = INIT;
always @(posedge CLK, negedge nRST) begin
if (!nRST)
nQ <= 1'b1;
else
nQ <= ~D;
end
endmodule

module GP_DFFS(input D, CLK, nSET, output reg Q);
parameter [0:0] INIT = 1'bx;
initial Q = INIT;
always @(posedge CLK, negedge nSET) begin
if (!nSET)
Q <= 1'b1;
else
Q <= D;
end
endmodule

module GP_DFFSI(input D, CLK, nSET, output reg nQ);
parameter [0:0] INIT = 1'bx;
initial nQ = INIT;
always @(posedge CLK, negedge nSET) begin
if (!nSET)
nQ <= 1'b0;
else
nQ <= ~D;
end
endmodule

module GP_DFFSR(input D, CLK, nSR, output reg Q);
parameter [0:0] INIT = 1'bx;
parameter [0:0] SRMODE = 1'bx;
initial Q = INIT;
always @(posedge CLK, negedge nSR) begin
if (!nSR)
Q <= SRMODE;
else
Q <= D;
end
endmodule

module GP_DFFSRI(input D, CLK, nSR, output reg nQ);
parameter [0:0] INIT = 1'bx;
parameter [0:0] SRMODE = 1'bx;
initial nQ = INIT;
always @(posedge CLK, negedge nSR) begin
if (!nSR)
nQ <= ~SRMODE;
else
nQ <= ~D;
end
endmodule

module GP_DLATCH(input D, input nCLK, output reg Q);
parameter [0:0] INIT = 1'bx;
initial Q = INIT;
always @(*) begin
if(!nCLK)
Q <= D;
end
endmodule

module GP_DLATCHI(input D, input nCLK, output reg nQ);
parameter [0:0] INIT = 1'bx;
initial nQ = INIT;
always @(*) begin
if(!nCLK)
nQ <= ~D;
end
endmodule

module GP_DLATCHR(input D, input nCLK, input nRST, output reg Q);
parameter [0:0] INIT = 1'bx;
initial Q = INIT;
always @(*) begin
if(!nRST)
Q <= 1'b0;
else if(!nCLK)
Q <= D;
end
endmodule

module GP_DLATCHRI(input D, input nCLK, input nRST, output reg nQ);
parameter [0:0] INIT = 1'bx;
initial nQ = INIT;
always @(*) begin
if(!nRST)
nQ <= 1'b1;
else if(!nCLK)
nQ <= ~D;
end
endmodule

module GP_DLATCHS(input D, input nCLK, input nSET, output reg Q);
parameter [0:0] INIT = 1'bx;
initial Q = INIT;
always @(*) begin
if(!nSET)
Q <= 1'b1;
else if(!nCLK)
Q <= D;
end
endmodule

module GP_DLATCHSI(input D, input nCLK, input nSET, output reg nQ);
parameter [0:0] INIT = 1'bx;
initial nQ = INIT;
always @(*) begin
if(!nSET)
nQ <= 1'b0;
else if(!nCLK)
nQ <= ~D;
end
endmodule

module GP_DLATCHSR(input D, input nCLK, input nSR, output reg Q);
parameter [0:0] INIT = 1'bx;
parameter[0:0] SRMODE = 1'bx;
initial Q = INIT;
always @(*) begin
if(!nSR)
Q <= SRMODE;
else if(!nCLK)
Q <= D;
end
endmodule

module GP_DLATCHSRI(input D, input nCLK, input nSR, output reg nQ);
parameter [0:0] INIT = 1'bx;
parameter[0:0] SRMODE = 1'bx;
initial nQ = INIT;
always @(*) begin
if(!nSR)
nQ <= ~SRMODE;
else if(!nCLK)
nQ <= ~D;
end
endmodule

module GP_IBUF(input IN, output OUT);
assign OUT = IN;
endmodule

module GP_IOBUF(input IN, input OE, output OUT, inout IO);
assign OUT = IO;
assign IO = OE ? IN : 1'bz;
endmodule

module GP_INV(input IN, output OUT);
assign OUT = ~IN;
endmodule

module GP_OBUF(input IN, output OUT);
assign OUT = IN;
endmodule

module GP_OBUFT(input IN, input OE, output OUT);
assign OUT = OE ? IN : 1'bz;
endmodule

module GP_PGEN(input wire nRST, input wire CLK, output reg OUT);
initial OUT = 0;
parameter PATTERN_DATA = 16'h0;
parameter PATTERN_LEN = 5'd16;

reg[3:0] count = 0;
always @(posedge CLK) begin
if(!nRST)
OUT <= PATTERN_DATA[0];

else begin
count <= count + 1;
OUT <= PATTERN_DATA[count];

if( (count + 1) == PATTERN_LEN)
count <= 0;
end
end

endmodule

module GP_POR(output reg RST_DONE);
parameter POR_TIME = 500;

initial begin
RST_DONE = 0;

if(POR_TIME == 4)
#4000;
else if(POR_TIME == 500)
#500000;
else begin
$display("ERROR: bad POR_TIME for GP_POR cell");
$finish;
end

RST_DONE = 1;

end

endmodule

module GP_SHREG(input nRST, input CLK, input IN, output OUTA, output OUTB);

parameter OUTA_TAP = 1;
parameter OUTA_INVERT = 0;
parameter OUTB_TAP = 1;

reg[15:0] shreg = 0;

always @(posedge CLK, negedge nRST) begin

if(!nRST)
shreg = 0;

else
shreg <= {shreg[14:0], IN};

end

assign OUTA = (OUTA_INVERT) ? ~shreg[OUTA_TAP - 1] : shreg[OUTA_TAP - 1];
assign OUTB = shreg[OUTB_TAP - 1];

endmodule

module GP_VDD(output OUT);
assign OUT = 1;
endmodule

module GP_VSS(output OUT);
assign OUT = 0;
endmodule

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