sayma_amc: make vivado timing analyzer happy

m-labs · Aug 17, 2017 · 3ada03f · 3ada03f
1 parent cd9c4d3
commit 3ada03f
Showing 1 changed file with 1 addition and 8 deletions.
diff --git a/misoc/targets/sayma_amc.py b/misoc/targets/sayma_amc.py
@@ -108,14 +108,7 @@ def __init__(self, *args, ethmac_nrxslots=2, ethmac_ntxslots=2, **kwargs):
         self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base,
                                ethmac_len)
 
-        self.crg.cd_sys.clk.attr.add("keep")
-        self.ethphy.crg.cd_eth_tx.clk.attr.add("keep")
-        # period constraints are required here because of vivado
-        self.platform.add_period_constraint(self.crg.cd_sys.clk, 8.0)
-        self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 8.0)
-        self.platform.add_false_path_constraints(
-            self.crg.cd_sys.clk,
-            self.ethphy.crg.cd_eth_tx.clk, eth_clocks.rx)
+        self.platform.add_platform_command("set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets eth_clocks_rx_IBUF_inst/O]")
 
 
 def main():