xilinx: fix Ultrascale IDDRE1 pin names

m-labs · Aug 17, 2017 · ddf5281 · ddf5281
1 parent 714c79e
commit ddf5281
Showing 1 changed file with 4 additions and 4 deletions.
diff --git a/migen/build/xilinx/common.py b/migen/build/xilinx/common.py
@@ -202,10 +202,10 @@ def __init__(self, i, o1, o2, clk):
         self.specials += Instance("IDDRE1",
             p_DDR_CLK_EDGE="SAME_EDGE_PIPELINED",
             p_IS_C_INVERTED=0,
-            i_d=i,
-            o_q1=o1, o_q2=o2,
-            i_c=clk, i_cb=~clk,
-            i_r=0
+            i_D=i,
+            o_Q1=o1, o_Q2=o2,
+            i_C=clk, i_CB=~clk,
+            i_R=0
         )